Embedded Files
Assembly Build And Characterization Of Test Board 7-Side F
Authors: Hendra Hartono and K. Srihari
Abstract: Test Board 7-side F is a multilayered test vehicle with sites for the assembly of stacked Chip Scale Packages (CSPs) and thin profile Ball Grid Arrays (BGAs). This report discusses the assembly process and issues related with the assembly of these area array devices on different pad sizes and surface finishes.
Packages BD and DE (stacked CSPs) and Package BH (extremely thin profile BGA) were assembled on Test Board 7-side F (TB7-F) using no-clean, eutectic Sn/Pb, Type 4 solder paste. The assemblies were characterized through electrical testing, x-ray, and cross-sectional analysis to inspect the integrity of the solder joints. The cause of assembly defects was also investigated.
Two time-zero failures were observed on Package BH due to incomplete developed solder masks on several pads at site F1 and F3. One cross-section shows that the solder mask completely covered the pad surface. Other cross-section shows that the solder mask partly covered the pad surface. Package BD and BE show that no time-zero failure. All of these packages pass the electrical testing.
Csp Assembly Build At Manufacturers' Services Limited (Msl)
Authors: Ursula Marquez and K. Srihari
Abstract: The primary goal of this project was the implementation of a "robust" CSP assembly process in a contract manufacturing environment. Four types of CSPs were assembled onto organic Printed Circuit Boards. The assembly process, including stencil printing process, component placement, and reflow soldering, was optimized through experimentation. The assemblies were characterized through x-ray analysis, cross-sectional analysis, and electrical testing. A total of 12 boards were assembled. No "time-zero" failures were observed in any of the assemblies. All the components exhibited good solder joint formation on both Electroless Nickel Immersion Gold (ENIG) and Copper Organic Solderability Protection (Cu-OSP) coated Printed Circuit Board pads. X-ray analysis of the assemblies showed no cases of solder bridging, misregistration, or opens.
Process Development And Mechanical Testing Of Csp Underfills
Authors: Murtuza Rampurawala and K. Srihari
Abstract: Chip Scale Packages (CSPs) are widely used in portable devices. They offer robust interconnects and higher standoffs in comparison to flip chips. CSPs in portable devices pose new reliability requirements due to the high mechanical stresses experienced during their service lifetime. The stresses are primarily generated due to impact, shock, vibration, mechanical bending, and thermally induced fatigue due to the CTE (Coefficient of Thermal Expansion) mismatch between the CSP and the Printed Circuit Board (PCB). These stresses can be greatly reduced by using an underfill material between the CSP and the PCB.
In this study, five distinct underfill materials were studied using six CSP package designs. The CSPs used for this study represent a range of components with different dimensions, construction, materials, etc. Various underfill dispensing patterns were studied. Initial analysis indicates that underfills may trap voids in high I/O fine pitch, perimeter arrays.
This study was aimed at evaluating the effect of underfill on the mechanical reliability of CSPs. Four of the five underfills tested performed satisfactorily when subjected to JEDEC (level 3) moisture / reflow preconditioning testing. Initial analysis shows that underfilled packages survive about 2–3 times longer than non-underfilled packages in torsion testing. None of the underfilled samples failed in vibration testing, while failures were recorded in non-underfilled samples.
Characterization Of Csptb-5 Assembly At Rockwell Automation
Authors: Arun Gowda, Hendra Hartono and K. Srihari
Abstract: Chip Scale Package Test Board #5 (CSPTB-5) is a double-sided, multilayered Printed Circuit Board (PCB). It incorporates sites for the assembly of CSPs, Ball Grid Arrays (BGAs), flip chips, and wafer scale packages. CSPTB-5 is designed for the study of various assembly variables including different pad sizes, pad geometries and routing configurations to determine their effects on assembly and reliability. CSPTB-5 was obtained from three vendors, Vendor J, Vendor AA, and Vendor AB. Test boards from these vendors were assembled at Rockwell Automation. Both tin-lead and lead-free assemblies were built.
X-ray inspection, cross-sectional analysis and standoff height measurements were carried out for the assemblies. Some of the defects observed were bridging, misalignment, opens, and excessive voiding. The defective assemblies were reworked and analyzed. The main causes of the defects were misalignment of the components and poor quality PCBs. Most of the PCB related defects observed were in assemblies with PCBs from Vendor AB. The PCBs from Vendor AB showed several cases of solder mask delamination and acute solder mask misregistration. The placement related defects were not specific to any particular vendor, but were related to component programming definition and errors associated with leadless CSPs and matrix tray tolerances.
Assembly And Reliability Of Reworkable Underfills For Csp Applications
Authors: Murtuza Rampurawala, Arun Gowda and K. Srihari
Abstract: Chip Scale Packages (CSPs) have found widespread use in hand held devices and portable electronics. Mechanical stresses induced by vibration and impact related shocks pose serious reliability concerns for CSP assemblies. Underfilling CSP assemblies can significantly increase their mechanical strength and robustness. The ability to rework CSP assemblies is of substantial importance considering the occurrence of assembly defects, field failures, and design changes. Reworkable underfills offer the advantage of reworkability over conventional underfills and are ideal for CSP applications.
Reliability studies were performed using accelerated testing methods on four different packages in combination with three underfills. The reliability data for non-underfilled assemblies, underfilled assemblies, and reworked underfilled assemblies are compared. Accelerated testing conditions using air-to-air thermal cycling (0 to 100oC, 20 minute cycle) and mechanical testing (cyclic torsion test) was used to compile reliability data. The samples were tested at 3.0 degrees of deflection in the torsion test.
Results indicate that underfilled samples survive approximately 3 to 10 times longer than non-underfilled samples in torsion testing. The cycles to failure varied depending upon the type of underfill and the package used. Reworking underfilled samples reduced reliability (in comparison to underfilled assemblies) by approximately 30 to 50% in torsion testing. Preliminary thermal cycling results have shown early failures in samples underfilled with the Hysol CNB-18 underfill material. Thermal cycling tests are still in progress (2300 cycles).
Tb7 Consortium Builds At Manufacturers' Services Ltd.
Authors: David Esler and K. Srihari
Abstract: This report summarizes the characterization of tin-lead assembly experiments conducted at Manufacturers’ Services Limited (MSL) in conjunction with the Research consortium group. Various component types such as Chip Scale Packages (CSPs), Ball Grid Arrays (BGA), leadless CSPs, Land Grid Arrays (LGAs), and Quad Flat Packs (QFPs) were assembled onto Chip Scale Package Test Board - 7 (CSPTB-7). The assembly experiments were carried out on different surface finishes, including Cu OSP, Electroless Ni/Immersion Gold (ENIG), Immersion Ag (ImmAg), Immersion Sn (ImmSn), and tin-lead Hot Air Solder Leveling (HASL).
The assemblies were characterized using electrical continuity tests, visual inspection, x-ray inspection, and cross-sectional analysis. There were four types of assembly-related defects that were observed in the surface mount assemblies, such as electrical opens, solder bridging, voiding, and solder balling. Time-zero failures were observed on a total of 66 components assembled on 22 printed circuit boards. A total of 17 assemblies had solder bridging defects, 43 assemblies had electrical opens, and 6 assemblies had excessive voiding. The details of the failures and their causes are included in this report. Relevant statistical analysis of assembly data is also provided.
Characterization Of Csptb-7 Build At Msl
Author: Mark Dunlap
Abstract: The purpose of this document is to provide information on the PCB builds that were conducted at Manufacturer's Services LTD on 10/11/01 through 10/12/01. MSL provided the assembly environment and staff as part of a joint Consortium build. The builds were conducted to assess the placement and process issues associated with high-count BGA packages and CSPs. Leadless components were also included to showcase the vision programming and process challenges that their unique construction entails. The design of test board seven made use of assembly variables including different pad sizes and geometry's along with pad surface metalization to determine their effects on assembly and reliability during post build life testing. A 1517 I/O BGA component was used to determine if the placement assembly process could yield good results with very high pin count components. Five different PCB surfaces, Ni/Au, OSP, Imm Sn, Imm Ag, and HASL was used in the assembly.
Reliability Of Double-Sided Assemblies: Part 1
Authors: Shiva Kalyan Mandepudi and K. Srihari
Abstract: High-density board level assemblies such as double-sided assemblies are gaining prominence with the decreasing size of electronic products. A critical issue in double-sided assemblies is the reliability of the device-to-board level attachment. In this research, the evaluation of thermal cycling reliability of double-sided assemblies is undertaken. Various scenarios, including mirror imaged double-sided assemblies, offset double-sided assemblies, and double-sided assemblies with different components on either side of the board are considered.
Plastic Ball Grid Arrays (PBGAs), flip chip Chip Scale Packages (CSPs), Quad Flat Packs (QFPs), and ceramic chip capacitors were assembled on 62 mil, multilayered FR-4 Printed Circuit Boards (PCBs) using eutectic Sn63/Pb37 solder paste. No assembly issues such as solder bridges, electrical opens or excessive voiding were encountered. The double-sided assemblies are currently in accelerated air-to-air thermal cycle testing. This report summarizes the assembly of the components and describes the tests planned to evaluate the reliability of the double-sided assemblies through thermal cycling.
Formation Of Voids In Bga Assemblies - Effect Of Different Solder Pastes And Reflow Profiles
Authors: Ursula Marquez, Arun Gowda, Hendra Hartono and K. Srihari
Abstract: Evaluating the solder joint integrity of Ball Grid Array (BGA) packages presents unique challenges. X-ray inspection becomes necessary to inspect the solder joints, which are hidden underneath the body of the BGA. During the reflow process, voids are formed by a variety of reasons including outgassing of flux and metal oxide reduction as shown in literature, please refer to "Factors that Affect Void Formation in BGA Assembly" [Primavera et alt., 1998]. The presence of voids in BGA solder joints can potentially reduce the mechanical robustness of the solder joint. The size, the location, and the number of voids in a solder joint may affect the reliability of the solder interconnect.
This report investigates the effect of solder paste on the formation of voids in BGA assemblies. The BGAs were assembled using five solder pastes, three reflow profiles, and four types of BGA packages. These parameters were evaluated to determine their effect on the formation of voids in BGAs, while past research showed a significant influence of paste on voiding [Primavera et alt., 1998], this experiment showed component type to have the most significant influence on void formation. The reflow profiles and the solder pastes did not have as a significant effect on the formation and size of the voids as the devices type. The presence and size of voids appeared to be a function of component type and solder sphere volume. One component type did not show any voids.
Solder Bumping For Ball Grid Arrays
Authors: Jeff Schake, Mohammad Yunus and K. Srihari
Abstract: Solder bumping is an important process step in the manufacturing of BGAs. In mainstream production, a highly robust solder bumping process is essential with requirements of rapid accurate deposition and uniform bump height distribution. Furthermore, this bumping process must be stable and produce high yields in order to support high reliability performance standards. Solder bumping of BGAs using different methods such as solder paste stencil printing and reflow, solder sphere attach with mini-stencil, and solder sphere stencil printing were studied. The bumping was performed for three reasons:
· To investigate alternative ball attach process methods.
· To facilitate building samples for evaluation of Pb-free solders (i.e. aging, shear testing, crack propagation, etc.).
· To allow the completion of Flip-Chip/BGA devices to evaluate the assembly of 1st and 2nd level variables.
Techniques of printing solder paste and mini-stencil sphere placement did not produce desirable results. However, the method of sphere printing has achieved excellent yields with eutectic Sn/Pb and other Pb-free alloy systems. This report outlines the research effort towards the development of a robust solder bumping process.
A Database Of Area Array Components
Authors: G.S.Nathan and K. Srihari
Abstract: The constructional features of any package widely influence the board design and assembly yields in the electronics assembly. This report discusses a software tool that serves as a knowledge base of constructional details of the area array components that have been characterized in the consortium effort. This software helps the design and process engineers to decide on a specific component construction to package the die. This report also serves as a user's manual for the application – ‘Component Browser’. It describes the installation procedure and the operational details of this software.
Authors: Ramasamy Muthaiyan and K. Srihari
Abstract: Accelerated reliability evaluation experiments have been conducted on numerous area array packages under the auspices of the research consortium at Universal Instruments Corporation. The data generated by these experimental efforts is extremely voluminous. Analysis of this large volume of data without a certain level of automation can be cumbersome. Therefore, a Reliability Module was designed and developed in order to effectively and efficiently analyze and maintain the data generated by the experiments that focused on the second level reliability of electronic packages.
The Reliability Module is a software tool that uses heuristics to search and sift through the extensive experimental data. The Reliability Module can search and retrieve the life cycle (reliability) and the experimental details (testing condition and assembly parameters) for any component for which reliability experiments have been performed. In addition, it can also estimate the life cycle of new components based on pre-existing data for similar components and tests.
This user-friendly Reliability Module was designed and programmed using Microsoft Visual Basic 6.0. A large body of information (both data and results) has been compiled and stored using Microsoft Access 2000, which serves as the database. The Reliability Module has “dynamic” help files, which can be accessed even during its execution by pressing the “F1” key.
This report provides ‘step-by-step’ information on how various features of the Reliability Module can be used and enables the user to fully explore the features of the software.
Estimation Of Warpage Of A Multi-Layered Substrate: A User's Manual
Authors: Manikandan Munikrishnan and K. Srihari
Abstract: The ability to predict the warpage of a multi-layered, high-density substrate has numerous implications on the design and material selection of the substrate. This report describes the software tool that has been developed to estimate the effective lamina properties and warpage of a multi-layered substrate. The application calculates the warpage using Plate Theory Equations based on the material properties input by the user. This report also serves as a user's guide for the application.
Authors: Murtuza Rampurawala and K. Srihari
Abstract: There has been a constant drive in the electronics industry towards high-performance and miniature products. These advances have led to many new packaging technologies, some of which are discussed in this report. The various package constructions that were studied include Flip Chip Chip Scale Packages (FCCSPs), Flip Chip Ball Grid Arrays (FCBGAs), Stacked Chip Scale Packages (Stacked CSPs), Wafer Level Chip Scale Packages (WLCSPs) and lead frame devices.
The packages were characterized through cross-sectional analysis, moisture absorption/desorption and moisture sensitivity studies, ball shear strength measurements, warpage, and Coefficient of Thermal Expansion (CTE) measurements. The moisture absorption studies were carried out by exposing the packages to temperature and humidity conditions of 30oC/60% RH. The moisture saturated devices were baked at 125°C and the loss of excess moisture from the packages was monitored. Moisture sensitivity studies were performed at lead-free reflow temperatures to study the effect of high reflow temperatures (260°C) on the integrity of the packages. The ball shear strength tests were performed using an Instronmaterials testing machine. The warpage and CTE measurements were obtained through the Shadow Moiré technique.
A package overview that includes, the internal and external dimensions is presented. In addition, results and inferences from the moisture sensitivity studies, the ball shear test, and the warpage and CTE measurements are also presented in this report.
All the Packages that were subjected to JEDEC level 3 preconditioning and three reflow cycles at 260oC peak temperature passed the failure criteria for the JEDEC level 3 testing. The results of the ball shear test showed ductile failures in all the packages.
"Characterization And Development Of A Flip Chip, Chip Scale Package (Fccsp) Generic Test Package"
Author: Martin K. Anselm
Abstract: Currently chip scale package (CSP) devices with 0.8mm pitch are common place and the number of I/Os is ever increasing. Most of these devices utilize eutectic tin-lead as the bump metallurgy, however similar sized packages must be produced with lead-free bumps due to the industry’s drive to remove lead from electronic devices.
The proposed tin-lead alternatives must be evaluated and compared to tin-lead before being used in production. Assembly and reliability issues are of primary concern, and this requires realistic test vehicles that address current package, pitch and bump materials and designs. A generic flip chip CSP test vehicle (FCCSP) was developed for this purpose.
Every aspect of the FCCSP bump and pad metallurgy is controllable, making it a very versatile and effective research tool. The component has potential for many areas of research beyond lead-free qualification such as CSP underfill, double-sided assembly reliability, and rework. The component has been used in several consortium builds.
Simple construction makes this component easy to produce in quantities sufficient for research projects. It is the intention of this report to outline the methods and process issues associated with the FCCSP's construction and to classify the package by IPC and JEDEC standards. Physical properties such as shear strength of the spheres and CTE of the component were also determined and the results are presented in this report.
Characterization Of Conductive Adhesives
Authors: Shiva Kalyan Mandepudi and K. Srihari
Abstract: Conductive adhesives are a potential replacement to solder for surface mount applications and thus need to be characterized in a similar manner. Spread, slump, tack and pull tests were conducted on six conductive adhesives. For the slump and the tack test, the IPC recommended procedures were adopted with minor modifications. Since a standard procedure was not available for the spread test, a spread test similar to one adopted in a previous study of solder paste was used. A procedure developed in house was used for the pull test.
Among the six conductive adhesives considered, two of them displayed superior slump characteristics when compared to the rest. These two could be considered for applications having pad spacings greater than or equal to 10.0 mils. The remaining four adhesives could be used for applications having pad spacings greater than or equal to 12.0 mils. Five of the six conductive adhesives tested had better tack properties than that of eutectic Sn/Pb type-IV solder paste. The spread observed for the conductive adhesives was not significant. Solder paste pull strength was greater than that of all the conductive adhesives.
Preliminary Evaluation And Assembly With Conductive Adhesives
Authors: Mohammad Yunus, Jaydutt Joshi, Jeff Schake and K. Srihari
Abstract: Electrically conductive adhesive technology is emerging as a potential replacement to lead based soldering. This report presents a brief introduction of the technology and some initial work done with conductive adhesive materials. The focus of this research was the evaluation of an isotropic conductive adhesive as a potential replacement for solder in fine pitch CSP technology, specifically for leadless devices.
A total of 64 leadless devices were assembled with conductive adhesive material and the assemblies were characterized based on their electrical continuity and standoff. Shear testing and pull testing was performed on the assemblies and their strengths compared to conventional Sn/Pb and Sn/Ag solder material.
Characterization Of Test Board #5: Vendor Aa And Vendor Ab
Authors: Ursula Marquez and K. Srihari
Abstract: Test Board #5 has been designed to study various issues concerning the assembly of Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Wafer Level CSPs (WLCSPs), and Micro Lead Frame (MLF) packages. In addition structures are designed into CSPTB5 to study the reliability of blind and buried microvias, effect of voids on the reliability of solder joints, and solder wettability and solderability.
This report provides a detailed characterization of Test Board #5 (CSPTB-5). Measurements of pad size, via size, and fiducial locations were made for the test vehicle. Three boards from Vendor AA and three boards from Vendor AB were chosen and the dimensional variations across each board and across different boards were evaluated. The evaluation showed differences between the design values and the measured values for both vendors. One vendor showed smaller pad dimensions and larger via dimensions as compared to the design. The other showed larger pad dimensions and smaller via dimensions as compared to the design. Also, the experiment showed variations in pad size and via size between boards and between sites.
Microvia Reliability Evaluation And Failure Analysis Of Csptb-5
Authors: Ursula Marquez, Arun Gowda and K. Srihari
Abstract: The increase in packaging density and the advent of fine pitch and ultra fine pitch area array components necessitates the use of multilayered boards and microvia structures to interconnect the components. The use of microvias as an interconnect structure is common today. Their reliability needs to be greater than that of the components on the assembly. This study evaluated the reliability of microvia structures on the microvia test site of CSPTB-5 supplied by Vendor AA and Vendor AB. Blind and buried microvias were considered along with various via and pad sizes.
This study is part of the on-going microvia reliability evaluation program at Universal Instruments Corporation. This report presents the results of the initial visual and electrical inspections, LLTS (Liquid to Liquid Thermal Shock) cycling data, and failure analysis. Several time-zero failures were observed in microvias from both vendors (Vendor AA and Vendor AB). For both vendors, vias between PCB (Printed Circuit Board) layers 1-2 performed the best in LLTS cycling. Various failure mechanisms were observed and are presented in this report.
An Overview Of Test Structures Designed Into Multilayer Microvia Test Vehicle Csptb-5
Authors: Jaydutt Joshi, Anthony Primavera, Madan Mohan Sitaraman and K. Srihari
Abstract: Chip Scale Package Test Board-5 (CSPTB-5) is a high density multilayer test vehicle. It consists of two microvia layers on the top as well as the bottom side. This report provides a detailed description of test vehicle design and construction. The test board contains assembly sites for high density Chip Scale Packages (CSPs), Direct Chip Attach (DCA) components, and microlead frame packages, some of which are routed using microvias in the component pads. This test board also includes microvia chains that will be used to evaluate the reliability of the bare board. Blind and buried via structures are constructed from layer 1 to layer 2, layer 2 to layer 3, and layer 1 to layer 3. This also provides a means to evaluate different via fabrication technologies with respect to via size and via pad size. In addition, CSPTB-5 contains test structures to evaluate the effect of void size on the reliability of the solder joints.
Overview Of Test Structures Designed On Csptb-6
Authors: Arun Gowda , Hendra Hortono, Ursula Marquez and K. Srihari
Abstract: Chip Scale Package Test Board – 6 (CSPTB-6) is a multi-layered high density Printed Circuit Board (PCB). It has two signal layers and two ground layers. CSPTB-6 is designed to facilitate the study of advanced component technologies and issues in the assembly and reliability of these components. This test vehicle includes test structures designed for the extensive study of CSPs, BGAs, QFPs, leadless CSPs, wafer level CSPs, passive surface mount capacitors and resistors, and lead-free components. CSPTB-6 design also incorporates test structures for the study of Pin-in-Paste (or AART) technology.
This report presents an extensive study of the design data of CSPTB-6. The various assembly sites and the components are described in detail. The characteristics of each assembly site including the pad diameter, the mask opening, the pitch, number of I/Os, and the package type are presented. In addition, the nature of study planned for a particular test structure is delineated.
Overview Of Test Structures Designed On Csptb-7
Authors: Ursula Marquez, Hendra Hartono, David Esler and K. Srihari
Abstract: Chip Scale Package Test Board - 7 (CSPTB-7) is a multilayered high density Printed Circuit Board (PCB) with two signal layers and two ground layers. CSPTB-7 is designed to study the assembly and reliability of Chip Scale Packages (CSPs), Ball Grid Arrays (BGAs) (up to 1517 I/Os), Quad Flat Packs (QFPs), and leadless CSPs. In addition, it is designed to study a variety of active components such as Subscriber Identity Module (SIM) connectors, Small Outline Packages (SOPs), Thin Small Outline Packages (TSOPs), Thin Shrink Small Outline Packages (TSSOPs), Small Outline Transistors (SOTs) and passive components. Beside these test structures, CSPTB-7 contains test sites for wetting studies of solder paste/spheres on different surface finishes and for the evaluation of shear strength of solder joints.
This report presents an overview of the design specifications such as pad dimensions, solder mask dimensions, component characteristics, and descriptions of the various test sites on CSPTB-7. The pad diameter, the solder mask openings, and the stencil apertures for side F of CSPTB-7 were measured, the summary of which is presented in this report. One board and 30 measurements per sites (6 sites) were considered. In most cases, the dimensions of the pads and the solder mask openings were smaller than the design specifications. On the other hand, the stencil aperture dimensions were larger than the design values.
Multilayer Microvia Reliability Evaluation And Failure Analysis
Authors: Jaydutt Joshi and K. Srihari
Abstract: This report summarizes the results of reliability evaluation and failure analysis performed on multilayer microvia interconnect structures. These were designed as a part of the CSP Test Board-5 (CSP TB-5), supplied by Vendor J. The reliability of the multilayer microvia interconnect structures was evaluated using Liquid-to-Liquid Thermal Shock (LLTS) testing. The microvias were fabricated using laser ablation technology and a non-reinforced dielectric. Samples were cross sectioned at time zero to evaluate the vias for parameters such as wall inclination, shape, and plating thickness. Resistance of the via chain was measured at intervals of 125 LLTS cycles. Samples that failed were subjected to non-destructive and destructive analysis in order to fully understand the failure mechanism. It was found that cracks at the via-pad interface were the major cause of failures.
Assembly Build Of Through Hole Components With Lead-Free Sn3.5ag Wave Soldering
Authors: Hendra Hartono, Dennis Barbini and K. Srihari
Abstract: Formation of lead-free through-hole solder joints was investigated as a part of the ongoing Research Consortium. Previous assembly experiments involving Alternative Assembly and Reflow Technology (AART) Test Board #1 did not include Sn/Ag solder alloy in the wave soldering build, Sn/Ag (96.5Sn/3.5Ag) solder alloy was utilized to assemble through-hole components in this study.
A variety of headers, phone jacks, D Shell connectors, latch connectors, and chip resistors were assembled on two test boards using a Sn/Ag wave soldering processes performed at Vitronics Soltec. The assemblies were characterized using the IPC-A-610C standard on acceptability of electronic assemblies. Visual inspection was performed to identify defects such as solder bridging, excess solder, insufficient solder, and unfilled-holes. Cross-sectional analysis was utilized to observe the solder joint and the fillet shapes.
In general, the wave soldered assemblies showed good results. In some cases, incomplete fillet formation on both the top and bottom sides of the Plated Through-Holes (PTHs) was observed. Voids and blow holes were observed in a few of the solder joints. Other defects include fillet lifting in Package TH5 assemblies on AART Test Board #1 and icicle formation on several pads and headers.
Lead-Free Assembly Of Generic Flip Chip Csp On Alternate Surface Finishes
Authors: Vinod Mohan and K. Srihari
Abstract: With the transition to a lead-free assembly process, there is a definite need to determine suitable surface finishes for printed circuit board metallizations that can replace Sn/PbHASL. Electroless nickel/immersion palladium (Ni/Pd), immersion Sn, and the lead-free HASLs – Sn/Ag, Sn/Ag/Cu, Sn/Cu and Sn/Ag/Cu/Sb are among the leading contenders for use with a lead-free process. The objective of this study was to determine the effect of the aforementioned surface finishes on the assembly and thermal fatigue reliability of a generic Flip Chip Chip Scale Package (FCCSP).
A 64 I/O, 0.8 mm pitch generic flip chip chip scale package with lead-free solder bumps was assembled on test vehicles with lead-free surface finishes using lead-free solder paste. The assemblies were tested for electrical continuity and thoroughly inspected using x-ray and cross-sectional analyses to check the integrity of the solder joints. One post-assembly electrical failure was observed, which was disturbed prior to reflow resulting in an open. Voids were located in several assemblies.
The test vehicles were subjected to accelerated air–to-air thermal cycling between 0 to 100oC. The air-to-air thermal cycle consists of 20 minute cycles with 5 minute ramps and 5 minute dwell times at the extreme temperatures. The assemblies have completed 4000 thermal cycles with first electrical failure on a component having Sn/Ag/Cu bumps and a Ni/Pd surface finish recorded at 3784 cycles.
Collapse Of Lead-Free And Eutectic Sn/Pb Solder During Bottom Side Pcb Assembly
Authors: Vinod Mohan, Shafi Saiyed and K. Srihari
Abstract: One approach to thermally enhance a BGA package is to attach a heat sink or heat spreader to the top of the component. However, the heat sink adds to the weight of the package and results in a reduction in standoff during topside PCB assembly. During the second reflow, an excessive package weight can cause elongation of the solder joint and possibly cause open joints.
The objective of this study was to determine the maximum package weight that could be supported by the surface tension of molten solder during the second reflow cycle. Lead-free and eutectic Sn/Pb solder pastes from one vendor were used. The lead-free solders were 95.5Sn/3.8Ag/0.7Cu and 96.2Sn/2.5Ag/0.8Cu/0.5Sb. Generic 256 I/O Flip Chip Ball Grid Arrays (FCBGAs) with lead-free and Sn/Pb solder bumps were assembled on CSPTB-6 test boards with immersion silver pad finish.
A package weight of 0.04 grams per solder bump caused the packages to fall off the PCB during the second reflow cycle. In all the cases, a package weight of 0.03 grams per solder bump significantly caused solder joint elongation. For lower package weights, 0.02 grams per solder bump and lower, the solder joints were elongated to varying degrees. Except for 95.5Sn/3.8Ag/0.7Cu solder alloy, a package weight of 0.02 grams per bump resulted in well formed spherical solder joints. In the case of 95.5Sn/3.8Ag/0.7Cu solder, the solder joints had not collapsed completely even when the package weight was 0.02 grams per bump.
Overview Of A Generic Flip Chip Plastic Ball Grid Array (Fcpbga) Package
Authors: Paresh S.Limaye and James M.Pitarresi
Abstract: A generic Flip Chip Plastic Ball Grid Array package (FCPBGA) is currently being developed at the Area Array Consortium at SMT Laboratory, Universal Instruments Corporation. In this package, global coefficient of thermal expansion (CTE) mismatch is generated between the PCB and the FCPBGA package by making the die almost as large as the substrate. This package shows a great promise as a test package for studying different assembly, board and substrate parameters as well as different solder alloys. The assembly process of the FCPBGA package involves bumping of the FR-4 substrate followed by dispensing of the encapsulant on the substrate. This is followed by the placement of a glass slide (in place of the actual Si die) on the substrate and finally the encapsulant is cured. The report also deals with some of the issues involved with the package i.e. warpage of the substrate and moisture sensitivity. Also some of the possible experimental applications of this package are discussed.
Lead-Free And Sn/Pb Assembly Of Leadless Chip Scale Packages
Authors: Vinod Mohan and K. Srihari
Abstract: Three different leadless Chip Scale Packages (CSPs) of 0.5 mm pitch were assembled on CSPTB-6 test vehicles with Cu OSP, immersion silver, and Electroless Nickel/Immersion Gold (ENIG) surface finishes. The assembly was carried out using tin-silver-copper (95.5Sn/3.8Ag/0.7Cu), tin-silver (96.5Sn/3.5Ag), and tin-silver-copper-antimony (96.2Sn/2.5Ag/0.8Cu/0.5Sb) solder pastes. In addition, the leadless CSPs were also assembled using eutectic Sn/Pb solder paste to serve as a baseline for comparison.
This report describes the assembly of three leadless CSPs: Package AL, Package AM, and Package AN. Package AL and Package AM have an exposed pad design that enhances the heat dissipation from the package. Only selected runs of the full factorial experiment were conducted in this experiment, since the other runs were conducted during previous assembly studies. All the assembled test vehicles were inspected using x-ray analysis, which showed several instances of voiding in the assemblies. The assemblies were tested for electrical continuity, followed by sample cross-sectional analysis, and the component standoff height measurements. There were two electrical opens on Package AL – both due to incorrect component orientation during placement. Air-to-air accelerated thermal cycling of the assemblies was carried out using a 30-minute, 0oC to 100oC profile. The assemblies have completed 4339 cycles with failures reported in Package AN and Package AL. An initial update of the reliability tests is included in this report.
Failure Mode Comparison Of Lead-Free And Eutectic Sn/Pb Solders In Flip-Chip Ball Grid Arrays
Author: Martin K. Anselm
Abstract: Three lead-free solder alloys and Sn/37Pb were used to construct and assemble flip-chip ball grid array (FCBGA) components for comparison of solder fatique crack behavior. These packages were subjected to air to air thermal cycling (AATC) in order to initiate and drive crack growth within the second level interconnections. The packages were then cross-sectioned and failure locations were identified. A primary goal of this document is to present fundamental differences and/or similarities between Sn/Pb and lead-free fracture surfaces.
Sn/37Pb solder joints subjected to accelerated thermal cycling tests typically fail due to fatigue crack propagation through the bulk solder. Although a crack may propagate through the Sn or Pb phases (transgranular-intragranular), fracture between phase boundaries is preferred (intergranular) [Kalpakjian, 1985]. This can either be due to very soft grain boundaries as compared to the bulk phase, the phase boundary contains a brittle phase, or the solder has become brittle due to liquid or solid metal embrittlement [Primavera, 2000]. During thermal cycling, growth of dendrites and subsequent coarsening of the joint increases the likelihood that the previous metallurgical phenomena can cause failure.
Lead-free alloys, with high Sn concentrations (95% or greater), contain less phase boundary area than eutectic Sn/Pb. The reduction in phase boundary area may require that cracks propagate directly through the Sn rich phases. If so, different failure mechanisms may exist which would have a profound impact on the thermal fatigue reliability of an assembly.
The differences between phase structures were characterized for the solder alloys with added attention to the solder joint characteristics in the crack region. Example images of the different phases and crack types will be presented as well as some predictions on possible effects on characteristic lifetime in air to air thermal cycling (AATC).
Lead-Free Rework Of Chip Scale Packages
Authors: Arun Gowda and K. Srihari
Abstract: A major concern during the assembly and rework of lead-free components is the relatively high temperatures that the components and the boards experience. The low standoff heights following assembly coupled with the solder joints being hidden underneath make inspection and rework of fine-pitch Chip Scale Packages (CSPs) challenging. Another major concern is the effect of rework on the neighboring components and the integrity of the Printed Circuit Board (PCB). These issues, coupled with the limitations imposed by the component, substrate (PCB), and the rework equipment to handle the higher lead-free reflow temperatures make the task of reworking lead-free assemblies more challenging.
Three different types of CSPs, all of similar configuration, number of I/Os, and pitch, having eutectic tin-lead (63Sn/37Pb), tin-silver-copper (96.3Sn/3.2Ag/0.5Cu), and tin-silver (96.5Sn/3.5Ag) solder balls were assembled and reworked. Different rework sequences and site redressing techniques were evaluated. The reworked assemblies were subjected to Air-to-Air Thermal Cycling (AATC) for reliability evaluation.
The copper coupon method of site redressing, which consists of reflowing residual solder to a roughened copper coupon, was superior in maintaining the integrity of the rework site during site redressing when compared to the soldering iron and wick method. The copper coupon method also resulted in higher standoff heights after assembly (component replacement) as compared to the soldering iron and wick method. The same rework profile was used for the rework of both the lead-free assemblies. There were no failures observed in any of the lead-free reworked assemblies after 2500 0°C-100°C AATC cycles (20 minute cycles). However, one tin-lead assembly failed at 1128 cycles. Previous testing of tin-lead bumped components (Package L) that were assembled on 62 mil thick Cu-OSP boards has shown first failures at around 900 cycles for assemblies on 15 mil pads [Fenton &Meilunas, 1999].
Lead Free Component Assembly Of Csptb-6 (Rockwell Automation)
Authors: Vinod Mohan, Hendra Hartono, Ursula Marquez, David Esler and K. Srihari
Abstract: As part of the Area Array Consortium test plan for lead-free solder development, a joint assembly build was undertaken at Rockwell Automation (Mequon, WI) in conjunction with the consortium group. This report summarizes the characterization of the lead-free assembly experiments conducted at Rockwell Automation. The details of the assemblies, assembly related defects and their analyses are provided. The assembly was conducted on CSPTB-6 test boards with different surface finishes. Various types of CSP components, BGAs, passive devices, and through-hole components were assembled.
Through-hole components were assembled using both an Alternative Assembly and Reflow Technology (AART) and wave-soldering processes. A comparison of the processes is provided wherever applicable. The solder paste used for the assembly was tin-silver-copper (95.5Sn/3.8Ag/Cu). Printability of the solder paste for fine pitch applications was evaluated by comparing the transfer efficiencies for a variety of aperture sizes and shapes. The wetting ability of the solder paste on the different surface finishes (immersion silver, Cu-OSP, and Electroless Nickel Immersion Gold (ENIG)) was studied by comparing the diameters of spread of the reflowed paste on metallurgical test sites provided on each test board. The ENIG surface was found to have the best wetting properties as indicated by a greater diameter of spread, among the surface finishes compared for this solder alloy. The Cu OSP surface finish however, had the most repeatable wetting as the diameter of spread had the least variation in the data. This is consistent with wetting studies performed in separate reports [Mohan & Srihari, 2002], [Yunus & Srihari, 2000].
The assembly was characterized by electrical testing, visual inspection, and x-ray inspection. The assembly defects were analyzed and the relevant statistics are provided in this report. The defects observed in the assembly of surface mount components included electrical opens, misregistration, exposed pads, incorrect orientation, and solder balling. The through-hole components had several defects such as solder balling, unfilled barrel, and insufficient fillet formation, for both the AART and wave-soldering processes. Some of these defects could be attributed to stencil design and component selection and/or characteristics.
Assembly Process Characterization For Pb-Free Through-Hole Soldering
Authors: Hendra Hartono, Mohammad Yunus, Mike Meilunas and K. Srihari
Abstract: As part of the lead free assembly experimentation performed by the Universal Instruments Research Consortia, the robustness of through hole solder joints was investigated. Comparison of wave soldering and Alternative Assembly and Reflow Technology (AART) or Pin-In-Paste (PIP) was performed to examine the process steps and resulting joint quality of lead free solder alloys. Several Pb-free solder alloys including Sn/Ag/Cu, Sn/Ag, and Sn/Cu were studied to compare the two methods in terms of the solder joint formation. In order to qualify the solder joint formed by each of these two methods, both destructive and non-destructive testing was performed. The results were then compared with a new solder joint standard guideline that was developed at Universal to judge the robustness of the solder joint that was formed. In addition, board warpage was measured to investigate the effects of the two soldering methods, on the quality of the board. This report details the investigation that was undertaken in comparing these soldering methods. It also discusses the effect of each soldering method in detail. The results indicate that while the lead free solder wave assembly process gave superior joint formation, the Alternative Assembly Reflow Technology method gave sufficient joint fillets in most cases.
Wetting Ability Of Lead-Free Solders In Nitrogen And Air Atmospheres
Authors: Vinod Mohan and K. Srihari
Abstract: This report summarizes the results of a set of experiments that were conducted to determine the effect of reflow atmosphere and profile on the wetting ability of 95.5Sn/3.8Ag/0.7Cu and 96.5Sn/3.5Ag solder pastes. Eutectic Sn/Pb solder paste was used as a baseline for comparison. Two different profiles - the traditional ramp-soak-ramp and a direct ramp (with no soak zone) - were compared for reflow in nitrogen as well as in air atmospheres.
The quality of the solder joints formed was characterized by determining the tendency to form solder balls, solder pull back, complete melting, the diameter of spread, and the shear strength of a sphere of solder reflown to a PCB pad. The maximum temperature difference across the leading and trailing edges of the board was also measured for the reflow profiles. The effect of pad size on the wetting ability of lead-free solders when reflowed in air using a direct ramp profile was also addressed. Through an analysis of variance (or ANOVA), it was found that the reflow atmosphere and profile have a significant effect on the wetting ability. For the flux systems considered, the direct ramp profile was found to perform better for reflow in air for lead-free solder compared to the ramp-soak-ramp approach. However, a reduced oxygen reflow atmosphere was found to give superior wetting and spread for lead-free alloys compared to reflow in air. In addition, the Sn/Pb alloy showed superior wetting compared to the lead-free solder alloys tested in any condition.
Wetting Problems On Immersion Sn Surface Finish
Author: Martin K. Anselm
Abstract: In the coming years, removing lead from the technology industry will require finding an acceptable lead-free solder as well as surface finish. Surface finish vendors will need a finish that does not deteriorate when shipped to their clients. These companies must also ensure that the surface produces the same reliable result as Sn/Pb HASL. Yet the complication does not stop there, an acceptable surface must have the same properties on a variety of solders since the standardization of a lead-free process will inevitably take a long time.
The immersion Sn process is very reproducible and reduces metallurgical complication since all major Sn/Pb replacement solders are Sn based. For this evaluation samples were evaluated that showed degraded solderability on several samples. In particular plated through holes (PTH) on some boards had not wet completely though while other boards showed proper solder fill. Comparison of the different boards on two different test build lots was performed.
Evaluation of the board surfaces showed the following differences: For boards that showed degraded wetting, there were evenly distributed scratch marks found across the top and bottom surface of array 2 boards 1 and 3 (A2B1, A2B3). A wetting test was done in order to determine if these scratches would effect diameter of spread of eutectic Sn/Pb solder. Second, board thickness variation may contributed to reduced wetting since there was an 8 mil difference in the thickness compared to the second set of samples. A typical industry standard for variation in board thickness has been quoted as +/- 10% or as high as +/- 7 mils on a 62 mil thick board regardless of layer count. This thickness variation may be significant where higher temperatures cause an increase in intermetallic formation and can in extreme cases cause desoldering to Cu and oxidation.
Authors: Vinod Mohan, Ursula Marquez and K. Srihari
Abstract: The effects of accelerated environmental aging on the thickness and wetting ability of immersion tin and immersion silver surface finishes were evaluated. This report includes the results of a set of experiments conducted to determine the variation in surface finish thickness and the wetting ability of test coupons subjected to aging at different temperature, humidity, and reflow conditions.
Samples from five vendors were considered for the thickness measurements. The effect of aging on the thickness of the pad finish was determined by subjecting the test coupons to different temperature and humidity conditions. Samples were aged at 155oC for one, two, and five hours and at 30oC / 60% Relative Humidity (R. H.) and 85oC / 85% R.H for one, four, and seven days each. In addition, the samples were subjected to multiple reflow cycles at Sn/Pb and lead-free reflow temperatures. The thickness was measured by using an X-ray Fluorescence (XRF) coating thickness measurement system (at Jabil Circuits) and by cross-sectional analysis using a Scanning Electron Microscope (SEM) (at Universal Instruments). There was significant variation in the thickness values acquired utilizing the two methods. The thickness measurements obtained from non-aged samples using XRF and SEM did not agree with the design specifications and vendor supplied data.
Samples from four vendors were considered for the wettability experiments. Wettability was determined through a solder sphere spread test. The effect of aging on the wettability of the surface finishes was determined by subjecting the coupons to different temperature and humidity conditions as mentioned before. Immersion tin coupons from Vendor A, with a design thickness of 15 micro inches showed the best wetting characteristics among the samples considered in this research. The majority of the samples showed reduced wetting ability when subjected to temperature and humidity aging. A general comparison between the immersion Ag and immersion Sn samples showed that the immersion Sn samples showed greater deterioration in wetting ability when subjected to different aging conditions. The immersion Ag samples evaluated showed more consistent wetting and were less susceptible to degradation due to environmental aging as compared to the immersion Sn samples.
Effect Of Temperature And Humidity On The Wetting Ability Of Alternate Surface Finishes
Authors: Vinod Mohan and K. Srihari
The pad finishes on printed circuit boards are susceptible to degradation due to environmental exposure during storage. This could adversely affect the solderability of the PCB pads, resulting in reduced assembly yields and second level reliability. The objective of this research was to determine the effect of temperature and humidity on the wetting ability of alternate surface finishes.
The surface finishes considered were electroless nickel/immersion gold (ENIG), Cu OSP, immersion tin, immersion silver, Sn/Ag/Cu HASL, and electroless nickel/immersion palladium. Test coupons with the aforementioned surface finishes were subjected to accelerated aging at 30oC/60% R.H. and 85oC/85% R.H. for one day, four days, and seven days. A spread test, using 30 mil preformed solder spheres of 95.5Sn/3.8Ag/0.7Cu alloy composition, was used to determine the wetting ability of the surface finishes. The results of the spread test for the aged samples were compared to that of un-aged samples.
It was observed that the wetting ability of all the surface finishes deteriorated when subjected to aging at 85oC/85% R.H.. Aging at 30oC/60% R.H. did not cause a significant reduction in wetting ability of any of the surface finishes except Ni/Pd and immersion Sn, which showed a reduced diameter of spread. Sn/Ag/Cu HASL finish was least affected by exposure to aging conditions of 85oC/85% R.H. for up to 7 days.
Authors: Michael Meilunas and Anthony Primavera
Abstract: The Area Array Consortium has begun an extensive lead-free evaluation program whose goal is to determine the thermal and mechanical reliability of selected lead-free solder alloys in electronics packaging. The information presented in this report is Universal Instruments’ portion of a round robin experiment conducted by IBM, Motorola, Nokia, Rockwell Automation and UIC. The ultimate goal of this experiment is twofold: The first goal is to determine if an area array assembly utilizing nickel pads on both the component and circuit board pads adversely affects the performance of BGA and CSP devices. Initial reliability issues have been identified and observed by three consortium members and has been documented in [Meilunas, 2000]. The second goal is to characterize the reliability of area array packages assembled with lead-free solder. This report contains up-to-date information concerning the thermal fatigue resistance of the chosen alloys used to assemble ball grid array (BGA) components to FR-4 printed circuit boards (PCB). Additionally, problems and issues associated with the components and alloys are discussed. Information pertaining to the assembly conditions, pre-test characterization, and test procedures are included in this report. Failure analyses and lifetime analyses are discussed, when applicable. This paper is a preliminary document provided to update consortium members on the status of the lead-free program at Universal and the information presented may or may not agree with that of the other round robin participants.
The Effects Of 150oc Thermal Aging On Lead-Free Bga Ball Shear
Author: Martin K. Anselm,
Abstract: Solder ball shear testing was used as a method of determining the mechanical robustness of Ball Grid Arrays utilizing lead free solder assembled to typical printed circuit boards (PCB's). The experiment was designed to characterize the ability of a solder joint to withstand external loading conditions that may exist in real world usage.
Three lead-free solders were used: Sn/3.5Ag, Sn/4.0Ag/0.5Cu, and Sn/2.5Ag/0.8Cu/0.5Sb (CASTINÒ) as well as Sn/37Pb as a baseline for comparison. Thirty mil solder spheres were assembled on PCB substrates with either solder mask defined or pad defined geometries. The solder mask defined (SMD) substrates were plated with electroless Ni / immersion Au (ENIG) or a copper organic soldering preservative (Cu OSP). The pad defined, or non solder mask defined (NSMD) geometry was plated with immersion Ag or CASTIN hot air solder leveling (HASL). The two geometries could not be compared due to different failure modes associated with the different solder joint shapes.
The various solder–pad combinations were shear tested following assembly and after thermal aging. Thermally aged samples were stored at 1500C and sheared at 250-hour intervals until 1000 hours.
Data was collected with an Instron load displacement machine, which was used to measure values such as maximum load and load at fracture, and to calculate values such as energy to break and energy to fracture. The data was used to determine the flow stresses of the various alloys on each metallurgy. The results of this test are presented in terms of alloy, pad and aging conditions.
Computing Crack Growth Rates In Lead-Free Solders Issues And Concerns
Authors: Michael Meilunas and Shiva Kalyan Mandepudi
Abstract: Finite Element Modeling and other methods that are used to predict BGA packaging reliability require material properties and descriptive (behavioral) equations for successful implementation. Tin-lead solder fatigue life estimations have been made possible by relating the temperature dependant elastic and inelastic properties of solder and the accumulation of damage within the solder to for a given thermal cycle to solder fatigue. One approach developed by Daveaux relates the solder fatigue crack growth rate to behavior to the plastic work density of the deformed crack region. This approach can be implemented in finite element codes to estimate the accumulation of damage for Sn/Pb eutectic solder within a BGA solder joint for a given thermal cycle.
Similar work is required to develop crack growth rates for lead-free solder alloys and to then relate those properties to a damage accumulation function. The work presented in this paper undertaken to measure crack growth rates for lead-free BGA devices. Air to air thermal cycling was used to drive fatigue within the solder joint. A dye penetration test was performed to measure crack sizes at selected thermal cycle intervals to correlate crack length with time at temperature.
Crack growth rate analysis was performed but conclusive crack growth rates were not formulated due to unforeseen issues regarding the crack behavior of lead free solders. During thermal cycling of the lead free samples, the dye penetrating fluid was not visible on cracked surfaces. Failure of the dye to coat crack surfaces prevented proper measurement of the crack areas. Cross-sectioning the BGA packages revealed that the cracks were extremely fine in nature and unlike those seen in typical tin-lead fatigue failures. This report presents the experimental procedure and describes the basic results and issues associated with the crack growth rate analysis.
Packaged Devices And Lead-Free Activities: Conclusions
Author: Anthony A. Primavera
Abstract: This report is a final overview and summary of the area array consortium activities related to assembly and test of packaged devices and additionally discusses lead-free soldering activities. This overview is a summary of the consortium development for the year 2000. A separate summary is presented in [Borgesen, 2002 – Optoelectronics Overview] for the year 2001 Opto-electronics program, and in [Blass, 2002 – Direct Chip Attach Program Overview] for the direct chip attach program. A total of over 50 reports have been prepared for the year 2001 area array efforts which discuss the following topics:
· Circuit Boards
· CSP/BGA Components
· Assembly
· Rework
· CSP and Reworkable Underfill
· Conductive Adhesives
· Reliability Testing
· Nickel Gold Metallurgy
· Lead-free Materials
· Lead-free Assembly
· Lead-free Reliability
Some of the projects completed this year were continuations of previous studies, such as thermal cycle testing, while other studies were started and completed within the 2001 work scope. Further information about each topic is available in supporting documents and reports, which are referenced in this report. Additional information is available in the year 2000, 1999 and 1998 Area Array Consortium CD-ROM. While activities included both tin / lead (Sn/Pb) as well as lead-free solder alloys, this overview will combine aspects of both technologies where important and relevant. For example, a discussion on rework or assembly will contain issues related to BGA and CSP devices for both lead bearing and lead-free solders. Issues related strictly to lead-free such as wave soldering with lead-free alloys, will be discussed as well.
Chip Scale Package - Past Assembly Data (Year 1998-1999)
Author: Anthony A. Primavera
Abstract: This report is an overview and summary of the previous assemblies performed during the years 1998 - 1999 Consortium. This information is included since the reliability test results for various CSP devices are now completed. Since vital assembly information is required to assess the reliability results, this data is provided for member companies that do not have access to the previous reports.
Mechanical Reliability Of Lead-Free And Mixed Csp Assemblies
Authors: Shiva Kalyan Mandepudi and K. Srihari
Abstract: Chip Scale Package (CSP) assemblies are widely used in various consumer electronics applications such as cellular phones. These assemblies are subjected to a variety of handling conditions, which may stress the second level interconnections. In this research, mechanical reliability was evaluated for various CSP assemblies by conducting accelerated torsion and vibration tests.
Two leadless CSPs, Packages AQ and AN, and two flip chip CSPs, Packages AU and AV, were assembled on multi-layered FR-4 Printed Circuit Boards (PCBs). These assemblies were subjected to torsion and/or vibration tests.
The torsion results indicate that Packages AQ and AN have comparable characteristic lives of approximately 3000 cycles. The characteristic life of Package AV was greater than that of Package AU by 400 cycles, which may be due to constructional differences that are discussed later.
The leadless CSP assemblies were subjected to a random vibration test with the frequency ranging between 10 to 1000 Hz for 32 hours. Failures were not observed in any of the assemblies.
Study Of Solder Joint Embrittlement For Nickel Gold Pad Finish (I)
Authors: Paresh S.Limaye and James M.Pitarresi
Abstract: Solder joints assembled on Nickel-Gold pad finishes have been known to exhibit a brittle behavior in shear testing after aging. To date speculative reasons for the problem have been suggested in literature, however no conclusive reason has been assigned as to the root cause of this embrittlement phenomenon. Most literature points to a ternary Ni/Sn/Au intermetallic [Cotts et al, 1999] [Mei, Z. et al, 1998].
In this experiment, nickel-gold plated boards from twenty-eight vendors were investigated with regard to the solder joint embrittlement phenomenon. The goal was to determine the board parameter(s) needed to predict the defect in a given board as well as survey the PCB industry for the occurrence of the phenomena. Initially, solder joint shear testing was conducted to see if any trends could be observed with respect to the mechanical properties of the joint, however no such trends were observed. It was also observed that the thickness of the nickel and gold platings in this experiment was not related to the occurrence of brittle failure.
SEM analysis revealed that all of the brittle samples analyzed contained very rough and uneven intermetallic layers and nickel, tin and gold were observed on the fracture surfaces. However, SEM analysis of the ductile samples revealed smooth and uniform intermetallic layers with only nickel and tin present. This indicates that the amount of gold-tin intermetallic located at the pad/ball interface in the ductile joint is relatively insignificant when compared to a brittle joint. Additionally, all the brittle failures observed before aging were attributed to improper fluxing and poor solderability to the printed circuit board pads. The SEM analysis has been carried out on a limited number of samples and further analysis is required. A second round of testing is proposed in which all the boards tested will have solder mask defined pads. This will reduce the amount of erroneous data present due to pad rip-offs from the board as the solder mask holds the pad in place and only the solder joint is sheared.
Nickel Gold Pad Finish Brittle Interfacial Fracture/Embrittlement Investigation: Part Ii
Author: Paresh Limaye
Abstract: Electroless Nickel/Immersion Gold (ENIG) is a commonly used pad finish in the electronics industry. This finish provides a flat solderable surface for further soldering and assembly operations. However, an early failure has been observed in the solder joints assembled on this finish in which the bulk solder delaminates from the intermetallic layer. To date, no conclusive cause for the occurrence of this phenomenon has been established. This research is an extension of a previous research project [Limaye, 2000].
CSP TB4 (Test Board 4) was supplied to 6 vendors for plating with ENIG finish. These boards were then bumped with Sn/Pb as well as Sn/Ag (96.5/3.5), Sn/Ag/Cu (95.5/3.8/0.7) and Sn/Ag/Cu/Sb (96.2/2.5/0.8/0.5) alloys. Samples were subjected to isothermal aging, LLTs and AATC. A shear test was performed on these to evaluate the solder joint strength, integrity and fracture surface.
No brittle interfacial fractures have been reported on any of the test combinations thus far. In general, the lead-free alloys show comparable or greater shear strength than the Sn/Pb alloy.
A case study was also carried out in which boards known to exhibit the brittle interfacial fracture were bumped with lead-free alloys. It was seen that Sn/Pb and Sn/Ag exhibited a partial delamination. However, Sn/Ag/Cu and Sn/Ag/Cu/Sb showed a clear ductile failure. However, the sample size for this case study is small. More intensive efforts need to be carried out to validate these findings.
Partial Underfilling Using The Four-Corner Attach Process
Authors: Murtuza Rampurawala and K. Srihari
Abstract: Chip Scale Packages (CSPs) in portable electronic applications require a higher mechanical reliability due to the high mechanical stresses of drop and shock compared to CSPs used in desktop applications. Underfilling CSPs provides a significant increase in the mechanical strength of the assembly, which improves resistance to stresses that are induced due to impact, torsion, and vibration.
Typically, a capillary flow underfill process is used to underfill the entire CSP package, which increases assembly process time significantly. A proposed alternative approach which utilizes dispensing underfill droplets only at the four-corners of the component was evaluated in this study. If proven successful, partial underfilling process would be ideal for applications where an increase in the mechanical shock resistance is a primary concern, and time cannot be allotted for a complete underfill process. In the partial dispense process, underfill was dispensed only at each corner of the package body, which resulted in a process time that was 50% less than a full underfill of the same device.
Reliability studies were performed using accelerated test conditions to compare CSPs assembled with no underfill, traditional full underfill and samples underfilled at the corners only. The packages were subjected to a cyclic torsion test at 3.0 degrees of deflection. An increase in reliability of approximately 1.5X to 2.0X was observed in partially underfilled Package Z (0.8 mm) pitch and Package AH (0.8 mm) pitch assemblies as compared to non-underfilled assemblies. A significant reduction of approximately 50 to 60% in the time to underfill was obtained for the partially underfilled samples when compared to fully underfilled samples.
Air To Air Thermal Cycle Testing And Failure Analysis
Author: Michael Meilunas
Abstract: According to IPC-SM-785, Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments, reliability refers to “the ability of a product to function under given conditions and for a specified period of time without exceeding an acceptable failure level”. The “product” may be an individual component, i.e. a BGA package, or an entire system, as in a cellular phone. In either case, the acceptable reliability of the product is predetermined by factors such as environment, usage, cost and time to obsolescence.
Only after reliability standards have been established should a product be designed and constructed. Knowledge of the reliability standards allows design teams to properly choose materials and assembly processes that, when completed, result in a product capable of performing to the set requirements.
Universal Instrument’s Area Array Consortium performs reliability tests on both the component and system level. Although numerous failure mechanisms exist, a primary interest is with the reliability of second level solder joints, which form the electrical and mechanical interconnections between electronic packages and printed circuit boards. Functionality loss of these joints is often cited as the dominant failure mode for products in service environments.
Although mechanical deformation may lead to solder fracture, studies have shown that most damage within the second level interconnects is due to stress formation and relaxation associated with differences in thermal expansion rates between package bodies and printed circuit boards. This wearout, or fatigue phenomenon, may require months or even years in an actual usage environment for completion and is highly dependent on the creep properties of the solder material. Obvious cost and time to market requirements make it impractical to test products over such lengthy periods.
Accelerated thermal cycling (ATC) offers a time and cost efficient means of testing products in a manner that exposes weak and marginal solder alloying, degradation of material interfaces and typically produces solder fatigue crack propagation in the second level solder joint. Air to air thermal cycling is a process in which products are cycled between two temperature extremes in a relatively short period of time. The temperature extremes, transition or ramp time, and dwell time are often based on specific reliability requirements or meet specific industry wide standards.
This paper discusses the capabilities of and procedures followed by Universal’s SMT lab to evaluate the ATC reliability of electronic assemblies including pre-test inspection, thermal cycling, post-test failure analysis and data (lifetime) analysis.
Reliability Modeling Of Area Array Packages
Authors: James M. Pitarresi, Narendra P. Singh and Anthony Primavera
Abstract: A finite element based approach for estimating the thermal cycling reliability for chip scale packages is presented. Three-dimensional finite element models were built for each of the packages studied. The methodology is based on Anand’s viscoplastic constitutive law for the solder response stress-strain response. To test the validity of this constitutive relation, the displacement in the solder joint for a generic CSP was predicted to within 20% of that measured using moiré interferometry. Darveaux’s crack growth-rate model for solder fatigue was used as the solder failure metric. A Weibull two-parameter failure distribution was assumed. The characteristic life of each package was estimated for the 0oC to 100oC, 20-minute cycle. Good correlation between the measured and predicted life was observed for many of the packages that have completed their testing. The correlation was typically within the expected
1.5X error band of the method. In addition, some packages were studied using field-use thermal profiles: one cycle per day 10oC to 45oC, one cycle per day 20oC to 60oC, and 16 cycles per day (90-minute) 20oC to 60oC. It was found that the acceleration factors for these cases were greater than fifteen times that of the 0oC to 100oC, 20-minute cycle. It was found that wafer-scale CSPs present new modeling challenges due to their small size and inclusion of thin material layers in the under bump metallurgy. Lead-frame packages also present challenges in that Darveaux’s crack propagation method was not developed for the type of solder joint that they generate. Further work needs to be done to improve the modeling results for these packages.
Reliability Testing Results Of Chip Scale Packages
Author: Michael Meilunas
Abstract: Evaluation of a CSP assembly’s performance involves the investigation of many factors including printed circuit board parameters, assembly techniques, package construction details and package materials. The typical in-field failure mechanism of a CSP is second level solder joint fatigue due to differences in thermal expansion between the component and printed circuit board. Thus, Universal Instruments utilizes accelerated air to air thermal cycling (ATC) to evaluate package reliability since ATC typically results in solder fatigue failures. This report will discuss current and recently concluded tests and is meant to append ‘Reliability Testing Results for Chip Scale Packages – Phase II’ of December 1999.
Authors: Michael Meilunas and Shiva Kalyan Mandepudi
Abstract: Air to air thermal cycling (AATC) is a means of evaluating the thermal fatigue resistance of BGAs and CSPs assembled to printed circuit boards (PCBs). Through the 2001 to 2002 consortium, Universal Instruments, in conjunction with Motorola (Austin), have combined resources to test over 20 package designs and 1500 components on a variety of PCBs. This paper discusses the AATC tests performed on BGA and CSP packages assembled to Test Board 6 (TB6) and Test Board 7 (TB7). Packages and test boards are briefly described with attention given to the design features that affect reliability. Information regarding the pre-test analyses, thermal cycles, event detection process, lifetime calculations and failure analyses is provided, if available.
Pull Test Evaluation Of Through-Hole Components Assembly
Authors: Hendra Hartono, Shiva Kalyan Mandepudi and K. Srihari
Abstract: Pb-free solder alloys being used in wave soldering and Alternative Assembly and Reflow Technology (AART) processes were evaluated for the robustness of through-hole solder joints formed. An experiment was performed to evaluate the strength of these Pb-free solder joints, with eutectic Sn/Pb assemblies used as a baseline for comparison.
Five types of headers were assembled on multi-layered, FR-4 Printed Circuit Boards (PCBs), with assembly parameters such as the Plated Through-Hole (PTH) diameter, pad size, and stencil aperture area being varied. The assemblies were built using eutectic Sn63/Pb37, Sn95.8/Ag3.5/Cu0.7, and Sn96.5/Ag3.5 solder alloys as described in [Hartono, 2001] and [Hartono, 2002]. The pull test was used to assess the strength of the through-hole solder joints.
The pull force of the AART assemblies using eutectic Sn/Pb and Sn95.8/Ag3.5/Cu0.7 alloys was comparable. However, Sn96.5/Ag3.5 wave soldered assemblies had higher pull force when compared to the Sn95.8/Ag3.5/Cu0.7 AART assemblies.
Site Redressing Techniques For Lead-Free Rework
Authors: Arun Gowda and K. Srihari
Abstract: The rework of area array components typically involves the removal of the defective component, site redressing, flux/solder deposition, and component replacement. This process is extremely challenging due to the hidden nature of the solder interconnects, the susceptibility of the Printed Circuit Boards (PCBs) to damage from multiple reflow cycles, and the extent of operator dependency. These issues are further aggravated when implementing a lead-free soldering process. The resulting processing temperatures are higher for lead-free alloys than for Sn/Pb eutectic solder which puts further constraints on the materials, and shrinks the process windows for successful rework. Site redressing involves the removal of excess solder and the preparation of the site for replacement with a new component. It is imperative that the solderability of the PCB site be well preserved during site preparation and is planar enough to provide successful component replacement. Some of the common failures of the site redressing process include solder mask damage and pad rip-off. These add additional process steps such as solder mask repair and pad repair, which in-turn add substantial costs to the assembly and may compromise the reliability of the assembly.
Three different site redressing techniques, the copper coupon method, the soldering iron and wick method, and the coupon wick method, were evaluated based on visual inspection of the redressed site, the height and shape of the residual solder on the pads after site redressing, and the time required for each technique. The three techniques were evaluated for three different test sites with different pitches and initial solder volumes.
The results of the experiments showed that there are numerous factors that need to be considered while selecting a site redressing method. Some of the important considerations are component pitch, PCB materials, operator expertise, throughput, and cost. The copper coupon method and the soldering iron and wick method were successful in redressing all the sites. There were some inherent issues in the coupon wick method, which resulted in its poor performance.
Rework Of Underfilled Chip Scale Package Assemblies
Authors: Arun Gowda, Murtuza Rampurawala and K. Srihari
Abstract: The underfilling of Chip Scale Package (CSP) assemblies offers a significant increase in the mechanical strength and robustness of the assembly. Underfilling a CSP will improve the second level interconnection's resistance to stresses induced by impact, torsion, vibration, and thermal fatigue. The reworkability of underfilled CSP assemblies is of substantial importance considering the occurrence of design changes, manufacturing defects, and field failures. Rework of underfilled CSP assemblies poses many challenges in terms of removal of the defective component and redressing of the site to remove the underfill and residual solder.
Rework processes were developed for four different packages in combination with four underfills. Thermal profiles for component removal and replacement were developed for all the underfills. Several automated sequences were attempted to remove components using an independent pick-up tube, but the vacuum force was insufficient to overcome the adhesion of the underfill between the component and the board. A modified removal sequence and manual twisting motion was required to remove the defective component. Site redressing was performed using a rotary tool and dental brush. The brushing was followed by removal of excess solder using the soldering iron and wick method. New components were placed on the redressed site and soldered. The reworked assembly was then underfilled.
A high level of operator involvement was required to rework the underfilled CSPs. The two Loctite 227576_A underfills (ver 1.0 and ver 2.0), which are two versions of the same underfill, could not be satisfactorily removed by mechanical brushing followed by residual solder removal using the soldering iron and wick method. Recommendations from Loctite Electronics for site redressing include site scavenging, which removes the residual solder and part of the underfill material, followed by mechanical brushing at 30000 rpm. Since a site scavenging system was not available during this study, a soldering iron and wick method was used to redress the sites. The use of the manufacturer's recommendations for site redressing may have resulted in the complete removal of the underfill material from the rework site.
Mechanical brushing followed by residual solder removal using soldering iron and wick method was successful in redressing rework sites assembled with Hysol and Emerson & Cuming underfills. CSP assemblies using both these underfills were successfully reworked.
The reliability of the reworked samples was evaluated through air-to-air thermal cycling and torsion testing. The results of the reliability are experiments are presented in Rampurawala, et al. [2002].
Rework Of Leadless Chip Scale Packages With Exposed Pads
Authors: Arun Gowda and K. Srihari
Abstract: The trend towards miniaturization and increased performance in telecommunication products requires the influx of component technologies that offer high functionality, small size and weight, and improved thermal and electrical performance. To address this need, component technologies with exposed center pads are being increasingly used for portable handheld applications. The die-attach paddle (exposed pad) in these components is exposed on the bottom surface of the package and provides enhanced thermal and electrical performance when soldered to the Printed Circuit Board (PCB). This research considers two fine pitch (0.5 mm) leadless Chip Scale Packages (CSPs). The issues in the rework of these fine pitch CSP assemblies are compounded by the very low assembly standoff and the large volume of solder that connects the exposed die-attach paddle of the package to the PCB pad. High reflow temperatures are required to remove and replace the components. In addition, high placement accuracy is required from the rework equipment to place such fine pitch devices. These devices do not offer a high degree of self-centering capability due to the non-collapsible nature of their terminations.
Two leadless CSPs, Package AM and Package AL, were considered for this study. These CSPs were assembled on multilayered PCBs with both tin-lead and lead-free (tin-silver-copper) solder pastes. The assemblies were characterized based on x-ray inspection, electrical resistance, and cross-sectional analysis. The tin-lead and lead-free assemblies were reworked using a hot gas rework station. The rework process was developed for both CSPs, with tin-lead and lead-free interconnections. The copper coupon and the soldering iron and wick site redressing methods were evaluated for the rework of these particular assemblies. The reworked assemblies were characterized in a manner similar to the characterization of the non-reworked assemblies.
The rework of the leadless CSP assemblies, both tin-lead and lead-free, posed challenges in the site redressing and component replacement processes. The soldering iron and wick method was found to be superior to the copper coupon method in redressing the rework sites. Several reworked assemblies had "time-zero" failures. These failures were primarily due to open joints, which were attributed to the incomplete reflow of the solder paste and insufficient solder paste deposition. An additional reflow cycle at elevated temperatures was able to correct the defects due to incomplete reflow of solder paste. Aggressive thermal profiles that exposed the component body to temperatures in excess of 265°C were required for the component replacement process. These reflow profiles may stress the components and endanger the integrity of the PCB rework site.
Authors: Antonio Prats and Daniel Blass
Abstract: Good soldering of a flip chip assembly in air was demonstrated with two of 11 paste fluxes, but only in a cooler profile, which had a soak of 152°C, about four minutes to the peak of 208°C, with 59 seconds over liquidus. These fluxes, Indium TAC023 and Kester R903, showed good soldering to the pads and good collapse.
In air with the hotter profile, five fluxes gave no electrical failures, but visual examination of the solder joints showed that none gave acceptable soldering. This profile had a soak temperature of 168°C, about four minutes to the peak temperature of 228°C, with 47 seconds over liquidus. Flux film thickness had no noticeable effect on soldering.
With the oxygen level adjusted to approximately 1000 ppm, five fluxes showed good soldering in the hotter profile. These were Almit BM1-RMA-NC, Alpha Metals CF2400, Indium TAC023, Kester 9603 and Kester R903.
Liquid fluxes seem to flux well in all profiles, but left too much residue to allow for underfilling. In many cases, there were problems with solder bridging. This problem may be alleviated by optimization of the flux jetting process.
Assembly Evaluation Of Jet Dispensed No-Clean Liquid Fluxes
Author: Antonio Prats
Abstract: This study evaluated the assembly of flip chips using 11 no-clean liquid fluxes applied with a DispenseJet system on an Asymtek Century 720 dispenser. Five of the fluxes volatilized very quickly after dispensing. Alpha Metals 9171 flux leaves a tacky film that holds the die securely onto the die site. The other four left a non-tacky film that would be unsuitable for a robust assembly process. The other six fluxes remain liquid through die placement.
The six liquid fluxes and two of the volatile fluxes were used for assembly. All eight showed good soldering. However, these fluxes had problems with solder bridging and excessive flux residue after reflow. For use in future trials, the jetting process can be optimized to reduce the amount of dispensed flux. This may alleviate some of the problems encountered with these fluxes.
Soldering Defects In Flip Chips Bumped With 95.5%Sn/4.0%Ag/0.5%Cu Lead-Free Alloy
Authors: Sunil Gopakumar and K. Srihari
Abstract: Earlier work with LF-2 (Sn/Ag/Cu) bumped flip chips indicated that good soldering could be achieved with a sufficient amount of flux. Using the same processes, recent work has been unable to produce consistently defect-free assemblies. The defects are improperly wetted solder joints that are not soldered to all wettable pad surfaces and poor self-centering of the chip. Higher levels of soldering defects occurred on Cu-OSP pads than Ni/Au pads. Since the chips and substrates used throughout the experiments were from the same lots, aging of the parts was considered as one of the possible reasons for the current soldering defects. The experiment here is part of an effort to assemble different Sn/Ag/Cu bumped chips onto various substrates to investigate soldering.
In this experiment, Sn/Ag/Cu bumped chips supplied by Bosch were assembled onto matching substrates with OSP-coated copper and Ni/Au pads. This alloy, 95.5Sn/4.0Ag/0.5Cu, is slightly different composition than the 96.5Sn/3.5Ag/1.0Cu LF-2 alloy from K&S Flip Chip Division. The defect trends were similar to the LF-2 bumped flip chips. Fewer defective solder joints were observed on Ni/Au pads than OSP-coated copper pads. On Ni/Au pads, 12% of the joints had wetting problems compared to 66% of the joints assembled on Cu/OSP. All chips assembled to the Cu/OSP pads had at least one defective joint while only half of the chips assembled to Ni/Au pads had defective joints. Despite the poor soldering, these chips soldered well enough that all parts were electrically continuous. In part, the good yield was a result of a substrate design that gives enough collapse of the solder bump onto the substrate pad.
Authors: Sunil Gopakumar, Sandeep Tonapi and K. Srihari
Abstract: Variations in the peak reflow temperatures for lead-free flip chip assembly could change the microstructure and composition of the solder joints. These changes can affect the mechanical properties and fatigue resistance of the solder joints. Previous reliability testing used profiles with peak temperatures of 238°C or 244°C and found that the joints formed in the hotter profile had slightly faster fatigue. This report investigates the effect of using higher peak reflow temperatures of 250°C and 260°C for assembly of LF-2 (95.5Sn/3.5Ag/1.0Cu) bumped flip chips and compares the result to the previously used profiles. The chips assembled with the 250°C peak reflow profile showed performance similar to the cooler profiles but the chips attached with the hottest reflow profile had a drastic reduction in fatigue resistance.
Effect Of High Temperature Reflow On Thermal Shock Resistance Of Lf-2 Bumped Flip Chip Assemblies
Authors: Sunil Gopakumar, Sandeep Tonapi and K. Srihari
Abstract: Packaged flip chips, such as flip chip BGAs, will see multiple reflows during package manufacturing and SMT attachment to the motherboard. The higher reflow temperatures used with lead-free solders presents challenges to existing printed circuit board and electronic packaging materials. These materials may not pass component qualifications tests such as JEDEC moisture/reflow sensitivity tests with lead-free profiles. Underfill-flux combinations that pass JEDEC Level 3 with a 220°C peak temperature may popcorn with peak temperatures of 240°C or higher.
For Sn/Ag/Cu bumped flip-chip-in-package, the multiple reflows bring some additional concerns. Variations in the reflow profile used to attach LF-2 bumped chips affect the solder joint properties and fatigue resistance and extra reflows could further decrease fatigue resistance. This possibility was explored by performing the JEDEC Level 3 test on some parts with high peak temperature reflow and then thermal shock testing the parts.
With a peak reflow temperature of 260°C, both underfills failed by the JEDEC Level 3 test because some chips had underfill delamination. The parts were still electrically testable and none had popcorned. Dexter FP4549 had fewer failures than Namics U8437-3. When Namics U8437-3 was JEDEC tested with a peak temperature of 244°C, no chips delaminated.
In subsequent thermal shock testing, the parts JEDEC tested with the 260°C peak temperature failed faster for all material sets. The JEDEC test causes a stronger reduction in thermal shock performance if the chip was attached to Ni/Au pads instead of Cu-OSP pads. JEDEC Level 3 with a 244°C peak temperature did not cause as big a reduction in thermal shock performance.
Interestingly, the chip attach reflow profile was sometimes more important than the reflow profile used in the JEDEC test. Chips that were attached with 260°C peak profile failed faster than chips that had been attached with a cooler profile and then JEDEC tested with the 260°C profile. The difference in time to 50% failure was more than 4000 cycles for Cu-OSP pads.
Soldering Defects In Lf-2 Bumped Flip Chips
Authors: Raghunandan Chaware, Sunil Gopakumar, Sandeep Tonapi, Nikhil Vichare and K. Srihari
Abstract: Early experiments in assembling Sn/Ag/Cu bumped flip chips indicated that good soldering could be achieved to Cu-OSP and Ni/Au pads in a nitrogen atmosphere. The process included dip fluxing the bumps into a 2 mil or thicker film of Kester TSF-6522, a Sn/Pb tacky no-clean flux. As more parts were assembled with this process, however, soldering defects were found. These defects were solder joints that did not completely wet the substrate pad and poor self-centering of the chip. This inconsistent soldering did not lead to any electrical defects with the test vehicle used, and no failures in subsequent thermal cycling were attributed to the poor soldering.
This report examines soldering defects in more than 500 LF-2 bumped flip chip assemblies built with different process variations. Chips were assembled with Kester TSF-6522 flux using flux thicknesses ranging from 1.4 to 2.6 mil. Four SMT-style reflow profiles were used to attach the chips. These profiles have soak stages, times above liquidus (217 °C) of between 54 and 71 seconds and peak temperatures from 238°C to 260°C.
Several trends were observed. First, LF-2 soldered much better to Ni/Au pads. There were 10 times more defects in the chips attached to Cu-OSP pads. In two processes used to build the largest number of chips, there were large variations in defect levels within each process. There did not appear to be any difference between the four reflow profiles. Sometimes, increasing the flux thickness appeared to increase the number of soldering defects. With no plausible explanation for such an effect, it is assumed this is a result of the small samples sizes and the large variations within each process.
Future work will examine new fluxes developed for Sn/Ag/Cu solder, alternative pad finishes, and reflow profile optimization.
Comparison Of Lf-2 Bumped Flip Chip Assembly With Sn/Pb And New Lead-Free No-Clean Tacky Fluxes
Authors: Sunil Gopakumar and K. Srihari
Abstract: Flip chips bumped with Sn/Ag/Cu lead-free alloys have not soldered as well as eutectic Sn/Pb bumped chips. Sn/Ag/Cu bumped flip chips assembled with fluxes developed for Sn/Pb have shown inconsistent soldering with poorly wetted joints, incomplete solder joint collapse, and sometimes poor self-centering.
This experiment investigated new fluxes developed for Sn/Ag/Cu solder alloys. LF-2 bumped chips soldered to blanket Cu-OSP or Ni/Au surfaces showed similar wetting and spread with both existing Sn/Pb fluxes and the new Pb-free fluxes. When soldering to flip chip pads, the lead-free fluxes gave fewer defective solder joints than the Sn/Pb fluxes but did not eliminate the soldering defects.
Multiple Reflows Of Lf-2 Bumped Flip Chips: Underfill Damage And Thermal Shock Performance
Authors: Sunil Gopakumar and K. Srihari
Abstract: Packaged flip chips, such as flip chip BGAs, will see multiple reflows during package manufacturing and SMT attachment to the motherboard. The higher reflow temperatures used with lead-free solders presents challenges to existing printed circuit board and electronic packaging materials. These materials may not pass component qualifications tests such as JEDEC Level moisture/reflow sensitivity tests with lead-free profiles. Underfill-flux combinations that pass JEDEC Level 3 with a 220°C peak temperature may popcorn with peak temperatures of 240°C or higher.
For Sn/Ag/Cu bumped flip-chip-in-package, the multiple reflows bring some additional concerns. Variations in the reflow profile used to attach LF-2 bumped chips affect the solder joint properties and fatigue resistance and extra reflows could further decrease fatigue resistance. This possibility was explored by performing a high peak temperature JEDEC Level 3 test before thermal shock testing. While the JEDEC parts failed faster, the result could be caused either by damage to the underfilled system during the JEDEC test or a change in the solder properties or both. The present experiment clarifies the issue by performing extras reflows either before or after underfilling.
This experiment investigated the effects of multiple reflows on the thermal shock resistance of LF-2 bumped flip chips. Extra reflows reduced the solder fatigue life by a factor a 5 or more for chips attached to Ni/Au pads and by a factor of 1.5 to 2 for chips attached to Cu-OSP pads. Whether the extra reflows occurred before or after underfilling also made a difference. When the assemblies were reflowed after underfilling there was also faster delamination. This shows that the extra reflows not only affected the fatigue resistance of the solder joints but also the damaged the underfill or the underfilled system.
Evolution Of The Microstructure Of Pb Free Solder On Various Metallizations
Author: Eric Cotts
Abstract: This report offers a review and critical analysis of our current knowledge and understanding of the behavior of Pb free solders of particular relevance to area array assembly. Emphasis is placed on intermetallic formation within solder joints and at the interfaces with typical contact metallizations.
Progress Report On No Lead Solder Studies
Authors: Lawrence P. Lehman and Eric Cotts
Abstract: No lead solders of Sn/Ag/Bi and Sn/Ag/Cu were examined for varying reflow and pad metallurgy conditions. We examined the formation and evolution of intermetallic phases within these systems and considered them in the larger context of joint integrity.
Assembly Of Lf-2 Bumped Pst2 Chips On Osp-Coated Copper Pads
Authors: Sunil Gopakumar and K. Srihari
Abstract: Earlier work with LF-2 (Sn/Ag/Cu) bumped flip chips indicated that good soldering could be achieved with a sufficient amount of flux. Using the same processes, recent work has been unable to produce consistently defect-free assemblies. The defects are improperly wetted solder joints that are not soldered to all wettable pad surfaces and poor self-centering of the chip. Higher levels of soldering defects occurred on Cu-OSP pads than Ni/Au pads. Since the chips and substrates used throughout the experiments were from the same lots, aging of the parts was considered as one of the possible reasons for the current soldering defects. The experiment here is part of an effort to assemble different Sn/Ag/Cu bumped chips onto various substrates to investigate soldering.
In this experiment, LF-2 bumped PST2 chips and matching substrates with Cu-OSP pads were supplied by K & S Flip Chip Division. Soldering results were similar to other recent experiments. There were many soldering defects such as poor self-centering and incomplete wetting of the substrate pad. The pad design, however, gave enough collapse to get electrically continuous assemblies.
Authors: Sunil Gopakumar, Sandeep Tonapi and K. Srihari
Abstract: The higher melting temperatures of the lead-free alloys necessitate the use of higher peak temperatures during reflow. Variations in the peak reflow temperatures and the time above liquidus could change the composition and microstructure of the solder joint. The resulting changes in the mechanical properties raise reliability concerns. This report investigates the effect of reflow parameters, namely the peak temperature and the time above liquidus, on the shear strength and thermal shock resistance of flip chip assemblies with the LF-2 solder alloy (95.5Sn/3.5Ag/1.0Cu).
In the first experiment, LF-2 bumped flip chips were attached with two reflow profiles. The non-underfilled chips were then sheared off to measure the strength of the solder joints. The longer, hotter profile gave slightly higher shear strength on Cu-OSP pads and significantly higher shear strength when soldered to Ni/Au pads.
In the second experiment, LF-2 bumped flip chips attached with the same two reflow profiles were tested in thermal shock. For both OSP and Ni/Au pad finishes these underfilled assemblies had lower fatigue resistance if attached with the hotter reflow profile. LF-2 joints on OSP pads had better fatigue resistance.
Overview Of Flip Chip Research For The 2001 Area Array Consortium
Author: Daniel Blass
Abstract: The past year’s research has covered a variety of topics in Sn/Pb and lead-free assembly, underfilling, and reliability.
Assembly investigations included flip chip in air, flux-jetting of liquid no-clean fluxes, flip chip assembly on to flexible circuits, reflow encapsulants, and lead-free assembly. Several fluxes solder well in air with cooler reflow profiles and more fluxes will solder with an oxygen level of around 1000ppm. Flux-jetting shows much promise. More work needs to be done but we now know what properties are desirable in a flux for this process. For reflow encapsulants, we focused on standardizing our approach and developed a first edition of a reflow encapsulant process “cook book”. Additional work with reflow encapsulants looked at board prebake and stencil printing.
Lead-free flip chip assembly presents several challenges. The assembly process developed previously did not prove robust in larger builds. The Sn/Ag/Cu bumped chips had varying levels of soldering defects. These defects, incomplete wetting of the substrate pads and poor self-centering, did not prevent solder joints from forming with the test vehicles used. More defects were observed with Cu-OSP substrate pads than with Ni/Au pads. This is unfortunate because chips attached to Cu-OSP pads performed better in thermal shock testing than chips attached to Ni/Au pads. The difference is generally attributed to the loss of copper from the solder alloy to the Ni-Sn intermetallics, although precipitate formation could also play a role. Thermal history also affected reliability as chips reflowed multiple times before cycling had reduced reliability. Again, this effect was greater on Ni/Au pads.
In preparation for lead-free assembly, we began testing flip chips to higher peak reflow temperatures in the JEDEC Level 3 test. Interestingly, when the gap under the chip was reduced to less than 1 mil, very few underfills could pass JEDEC Level 3 with a peak temperature of 240°C and many failed at 220°C. With a 2 mil gap, 23 underfills were tested with a peak temperature of 240°C. In that test, most of the failures were with so-called “snap-cure” underfills.
Underfilling studies looked at self-filleting of the underfill. The type of flux usually affected whether an underfill self-filleted well. The underfilling of flip chip assemblies with trench solder mask openings was also studied. There is a tendency to form underfill voids in the trench openings between solder joints when the underfill flows parallel to the trench. During thermal excursions, these voids can lead to solder extrusions and bridging failures. While a convenient substrate design, the use of a trench design needs to be carefully considered and may not be appropriate for some applications. Work also continued on transfer molding of flip chips, a process attractive for component manufacturers. Defect-free transfer molding has not yet been obtained but reliability of molded parts is comparable to capillary flow underfills.
Reliability testing mostly focused on fillet cracking studies. These efforts will be used to develop ways to accelerate fillet cracking and relate the results to milder service conditions. A large experiment exposed flip chip assemblies to various moisture and aging conditions prior to thermal shock testing. The experiments found that fillet cracking initially decreases with moisture exposure but longer exposures accelerate cracking. Also, simply storing samples in dry nitrogen for 3 months gave increased fillet cracking over no preconditioning. Another experiment developed methods to measure crack growth in a model underfill. The initial results found that crack growth had an exponential power relationship to the strain energy release rate.
Assembly Evaluation Of 3m Uf3400 Reflow Encapsulant
Author: Antonio Prats
Abstract: This report documents the evaluation of U3400 reflow encapsulant from 3M. This is a high viscosity material and requires high placement forces and long hold times for successful assembly. Some die floated and failed to solder properly with settings as high as 500 grams of force and 400 milliseconds of hold time. The material can be dispensed by hand or with a positive displacement pump, but an auger pump creates bubbles. Soldering defects were seen with a profile that had a longer, high temperature soak, but not with a shorter soak at high or low temperature. Due to the required placement settings, UF3400 is not competitive for high throughput flip chip assembly.
Assembly Evaluation Of Kester 9101 Reflow Encapsulant
Author: Antonio Prats
Abstract: Kester 9101 is a reflow encapsulant that has been used frequently in previous studies for its relatively wide reflow process window and good reliability. It is designed for flip chip assembly with standard SMT profiles, and requires a secondary cure for 30 minutes at 160°C. It exhibited good soldering with all tested reflow profiles. These profiles had soak temperatures ranging from 154°C to 172°C, peak temperatures from 208°C to 233°C, and times to peak from 216 to 273 seconds. This material showed no placement related defects with the default placement parameters of 150 grams of placement force and 30 milliseconds of hold time. Acoustic microscopy showed voids in the underfill, an indication that a two hour bakeout at 125°C is not sufficient for this material on a 62 mil thick board.
Assembly Evaluation Of Kester Lx2-2-13 (Se-Cure 9125) Reflow Encapsulant
Author: Antonio Prats
Abstract: Kester LX2-2-13 (now called 9125) is a reflow encapsulant designed to fully cure within standard SMT profiles. It exhibited good soldering with all tested reflow profiles. These profiles had soak temperatures ranging from 154°C to 172°C, peak temperatures from 208°C to 233°C, and times to peak from 216 to 273 seconds. This material showed no placement related defects with the default placement parameters of 150 grams of placement force and 30 milliseconds of hold time.
Assembly Evaluation Of Alpha Fry Technologies Nuf 2071e Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari
Abstract: Alpha Fry Technologies NUF2071E is a reflow encapsulant designed for flip chip assembly. Die were assembled with three reflow profiles, Alpha Fry Technologies’ recommended profile which had a low soak temperature and two “standard” SMT profiles with low-temperature soaks. Alpha Fry Technologies NUF 2071E fluxed and soldered well in each profile. Underfill voiding, however, was observed in all die. With the two standard profiles, the voids even caused some electrical opens by pushing the chip away from the substrate pads during reflow.
Assembly Evaluations Of Emerson & Cuming Bga/Csp Reflow Encapsulants
Author: Antonio Prats
Abstract: Emerson & Cuming 11129‑152C and JS11156‑24 are experimental reflow encapsulants designed for BGA/CSP applications. They both exhibit good soldering with all tested reflow profiles in a soldering trial with flip chip assembly. These profiles had soak temperatures ranging from 154°C to 172°C, peak temperatures from 208°C to 233°C, and times to peak from 216 to 273 seconds.
11129-152C was used to assemble an 8 mm CSP and a 27 mm BGA. There were no placement related defects assembling the CSP with 1000 grams of force and 30 ms of hold time, or assembling the BGA with 1500 grams of force and 100 ms of hold time. There were some opens with the BGA due to a combination of component warpage and material gelling. The warpage increased the distance between the corner solder balls and their pads, and thin layer of material would occasionally cure over the pad before the other solder balls could collapse sufficiently to bring the ball in contact with it.
Bga/Csp Assembly With Reflow Encapsulants
Author: Antonio Prats
Abstract: A 27 mm BGA and an 8 mm CSP were assembled using three reflow encapsulants, Emerson & Cuming 11129‑152C, Kester 9101, and Dexter Hysol FF2200. The low viscosity of Kester 9101 made it unsuitable for the larger component, as the dispensed encapsulant would flow all over the substrate.
Bakeout of the substrate and components is important; two hours at 125°C was sufficient. All materials had a large amount of placement voiding. 11129-152C showed more ability to eliminate these voids during reflow than the other two encapsulants.
There were no electrical failures with the CSPs with any of the three materials. 18% of the BGAs did not form solder joints in the outer row of balls, caused by a combination of warpage and gelling of the encapsulant.
Assembly Evaluation Of Dexter Hysol Ff2000 Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari
Abstract: Dexter Hysol FF2000 is a reflow encapsulant designed for flip chip assembly that requires no post-curing cycle. It exhibited good soldering with the tested reflow profiles of no soak or low soak temperatures and short soak durations. Some reflow profiles with higher soak temperatures resulted in poor soldering due to the gelling of the encapsulant before solder joints could form. Die were assembled with six reflow profiles, Dexter’s recommended profile with no soak and five “standard” SMT profiles. The recommended reflow profile had a direct ramp-up to a peak temperature of 228°C with only 110 seconds to 183°C. The five standard reflow profiles had soak temperatures ranging from 156°C to 170°C, peak temperatures from 208°C to 229°C, and times to 183°C from 189 to 236 seconds. No placement related defects, die floating or shifting were observed with the default placement force and hold time. No underfill voids or fillet bubbles were observed in any of the assemblies.
Assembly Evaluation Of Dexter Hysol Ff2200 Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari
Abstract: Dexter Hysol FF2200 is a reflow encapsulant designed for flip chip assembly. In an initial screening, it exhibited good soldering with ten reflow profiles. These profiles had soak temperatures ranging from 154°C to 172°C, peak temperatures from 208°C to 233°C, and times to 183°C from 183 to 241 seconds. No placement related defects were observed with the default placement settings. Only one underfill void was observed with acoustic microscopy but bubbles were observed in the fillets around the chips.
Jedec Testing Of No-Flow Underfills At 240"C Peak Reflow Temperature
Authors: Felix Bruno and K. Srihari
Abstract: With the expected migration to lead-free solders, circuit boards and surface mount components will have to endure much higher reflow temperatures. With peak reflow temperatures of as much as 260°C, components will have to be qualified at these temperatures with the JEDEC Level Moisture Sensitivity tests and existing material sets may have to be modified. This experiment is part of a series of experiments to identify the underfill-flux combinations that will pass JEDEC tests with lead-free reflow profiles.
Eutectic Sn/Pb Flip chip assemblies were built with three different no-flow underfills, Dexter FF2200, Kester 9101, and Kester 9125. The assemblies were subjected to JEDEC Level 3 (J-STD-020A) testing with a peak reflow temperature of 240°C. After the JEDEC test, the assemblies were examined for underfill delamination and solder extrusions. No parts failed electrically and no parts had delamination. No extrusions were found with the Kester 9101 no-flow underfill. Kester 9125 averaged about 1 extrusion per chip and Dexter FF2200 averaged 5 to 6 extrusions per chip. No solder bridges were observed.
Assembly Evaluation Of Loctite X237115 Reflow Encapsulant
Authors: Ji Hyon Mun, Antonio Prats and K. Srihari
Abstract: Loctite X237115 is a reflow encapsulant designed for flip chip assembly. It exhibited good soldering with the tested reflow profiles of low to medium soak temperatures. Some reflow profiles with higher soak temperatures resulted in poor soldering due to the gelling of the encapsulant before solder joints could form. The profiles used had soak temperatures ranging from 154°C to 172°C, peak temperatures from 208°C to 233°C, and times to 183°C from 183 to 241 seconds. No placement related defects, die floating or shifting, were observed with the default placement hold time. Underfill voids were not observed on substrates that had been baked out before assembly.
Substrate Bakeout Experiments For Reflow Encapsulants
Authors: Ji Hyon Mun, Felix Bruno, Daniel Blass, Antonio Prats and K. Srihari
Abstract: Flip chip assemblies built with ten reflow encapsulants were examined to study the bakeout requirements for reflow encapsulants. A standard 2 hour bakeout at 125°C was not sufficient for several reflow encapsulants, including Kester 9101. One reflow encapsulant, Emerson & Cuming XNF 1500, could be assembled onto boards with a pre-bake of just 15 minutes at 125°C. As an alternative, drying with a reflow before assembly was used with Kester 9101. Four reflows with a peak temperature of 220°C or one reflow with a peak temperature of 240°C was able to prevent voiding with a 31 mil thick board. The results show that the bakeout requirements for reflow encapsulants can vary greatly and may also depend on the substrate construction.
Stencil Printing Of Reflow Encapsulants
Authors: Jeff Schake and Antonio Prats
Abstract: The substitution of a stencil printing process for the more common dispensing operation to deposit reflow encapsulant material in a flip-chip assembly test has resulted in achieving equivalent assembly yield performance, assessed by electrical continuity testing, x-ray inspection, cross sectioning, and C-SAM imaging. The reflow encapsulant materials used were not altered from their original low viscosity dispensing formulations in order to test the feasibility of stencil printing these standardized commercially available products.
Assembly Evaluation Of Sumitomo 4700a Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari
Abstract: Sumitomo 4700A is a reflow encapsulant designed for flip chip assembly. It exhibited good soldering with the ten reflow profiles for which it was evaluated but the experiment found other problems. Many underfill voids and voids around the solder joints were observed. The reflow encapsulant was not stable after the assembly and curing. The bubbles in the fillets around the chip, observed immediately after assembly, could migrate and grow in subsequent thermal excursions. This led to poor reliability in thermal cycling.
"Assembly Evaluation Of A Filled Reflow Encapsulant, Sumitomo 4750a"
Authors: Ji Hyon Mun and K. Srihari
Abstract: Sumitomo 4750A is a filled reflow encapsulant designed for flip chip assembly. It provided good fluxing and soldering with a variety of reflow profiles but the presence of filler particles caused soldering defects. Filler particles could be trapped between the solder bumps and the substrate pads and this would prevent the solder bumps from soldering to the pads. Underfill voids were also observed in many of the assemblies.
Reflow Encapsulant Codification: 2001
Author: Antonio Prats
Abstract: This is designed as a companion to the Underfill Process Codification. The aim is to present a guide to reflow encapsulant evaluation and process development. The focus here will be to highlight the differences, and to provide some simple and relatively quick characterizations that are necessary for reflow encapsulants. However, this should not be taken to mean that the establishment of a detailed and broad knowledge base is not important. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications. This document will also provide guidance for more detailed tests that will help with process development.
Effects Of Moisture And Aging On Underfill Fillet Cracking
Authors: Nikhil Vichare, Sakethraman Mahalingam and K. Srihari
Abstract: Fillet cracking is a common and sometimes dominant failure mechanism in thermal cycling of flip chip assemblies. Corner fillet cracks lead to fatal underfill delamination that starts at the chip corners. This corner delamination causes solder joints in the delaminated area to crack and fail. Fillet cracking strongly depends on the fillet thickness, the underfill, substrate mechanical properties and thickness, flux choice, and the moisture exposure and aging history of the parts. The present experiments were performed to learn how fillet cracking is accelerated by various moisture and aging preconditions. The conditions were also chosen to provide insight into the separate contributions of aging and moisture. These experiments represent early steps towards the extrapolation of accelerated testing results to reliability in service.
Three underfills, Dexter FP4549, Namics U8437-3, and Honeywell JM8802 were used with two no-clean fluxes, Kester TSF-6522 and Indium NC-SMQ 75. About 1000 flip chips were exposed to different moisture/aging preconditions and then subjected to Liquid-to-Liquid Thermal Shock (LLTS) testing. The moisture/aging preconditions were 72 and 144 hours of PCT, 85°C–30% R.H. for up to 3 weeks, 85°C–85% R.H. for up to 3 weeks, laboratory ambient for 3 months, dry nitrogen for 3 months.
The Pressure Cooker Test (PCT) provided considerable acceleration of fillet cracking and underfill delamination. There is some concern, however, that the PCT conditions and effects on the flip chip are too harsh to be useful.
The effects of 85°C–30% R.H. and 85°C–85% R.H. varied according to the underfill and flux. With Dexter FP4549, 85°C–30% R.H. often initially gave a decrease in cracking compared to no preconditioning. 1 and 2 weeks of 85°C–30% R.H. often gave similar cracking rates and rarely showed more cracking than no preconditioning. With 3 weeks of 85°C–30% R.H. there was an increase in fillet cracking over no preconditioning. Similarly, 85°C–85% R.H. sometimes gave an initial decrease in cracking after a 1 week exposure. 2 and 3 weeks generally gave more fillet cracking with 3 weeks of 85°C–85% R.H. giving the most acceleration. Flux was an important consideration as the acceleration of cracking depended on the flux choice. With 3 weeks of 85°C–30% R.H., for instance, FP4549 cracked more with the Kester flux, but with the other flux it had more cracking with 3 weeks of 85°C–85% R.H.
85°C–30% R.H. gave little acceleration of cracking for Namics U8437-3 but 85°C–85% R.H. gave considerable acceleration. A one week of exposure to 85°C–85% gave faster fillet cracking compared to non-preconditioned samples, but longer exposures did not necessarily make cracking worse for the Namics.
Neither 85°C–30% R.H. or 85°C–85% R.H. accelerated fillet cracking for Honeywell JM8802. The Honeywell fillets were relatively thick and even the non-preconditioned control samples cracked quickly. Similar to the Dexter, exposures to 85°C–30% R.H. actually decreased fillet cracking. Cracking after 85°C–85% R.H. preconditioning was comparable to the control samples. No effect of flux was observed with the Honeywell.
Aging for 3 months in the laboratory ambient or nitrogen gave some interesting results. For most of the underfill-flux combinations, 3 months in nitrogen gave more fillet cracking than either ambient aging or no preconditioning. The ambient aging usually gave less cracking than no preconditioning except for Namics U8437-3. The Namics also showed a clear flux preference as the Kester flux gave faster cracking than the Indium with 3 months in either aging condition.
There does not appear to be a single best choice for accelerating fillet cracking, an indication that multiple mechanisms are at work. Three basic effects are observed. Aging of the polymer without moisture increased fillet cracking. Aging in moisture initially gives a decrease in cracking. After some point, continued exposure will accelerate fillet cracking. The problem is that the point where cracking is accelerated is going to vary based on the condition and the material set. To put it simply, the effects of each moisture/aging condition were not consistent across the material sets. The future addition of cracking results for longer aging times should help refine the needed level of acceleration. It is likely that data will be needed for several accelerated conditions to properly extrapolate cracking for a given material set.
Jedec Level 3 Testing Of A Very Fine Gap Size Flip Chip Assembly
Authors: Felix Bruno and K. Srihari
Abstract: With the expected migration to lead-free solders, circuit boards and surface mount components will have to endure much hotter reflow temperatures. With peak reflow temperatures of between 240°C to 260°C, components will have to be qualified at these temperatures with the JEDEC Level Moisture Sensitivity tests. For flip chip, the hotter reflow temperatures will likely reduce the number of underfill-flux combinations that can pass JEDEC Level 3. This experiment is part of a series of experiments to identify underfill-flux combinations that will pass JEDEC tests with lead-free reflow profiles.
In the present experiment, a flip chip with a very fine gap (less than 1 mil) was used to test 12 underfills in combination with 4 no-clean paste fluxes, Heraeus TF38, Indium FC-NC-LT-C, Kester TSF-6502 and Kester 9603. Normally, most of these combinations would pass JEDEC Level 3 with a 220°C peak temperature. With this gap, however, only half of the combinations passed with no underfill delamination. Only 3 of the 12 underfills passed with all 4 fluxes, Honeywell JM8802, Kester 9203, and Sumitomo 4300A. With a peak temperature of 240°C, all but 4 combinations failed JEDEC Level 3. The passing combinations were Honeywell JM8802 with Kester TSF-6502 and Sumitomo 4300A with the Indium and two Kester fluxes. Emphasizing the effect of the small gap in this experiment, many of the failing combinations have passed JEDEC Level 3 with a 240°C peak temperature with a 2 mil gap under the chip.
Authors: Nikhil Vichare and K. Srihari
Abstract: The present work discusses the formation of solder extrusions and bridging in various underfill-flux combinations. Chips were attached to a substrate with pads defined by a trench solder mask opening. Two underfills, Dexter FP4548 and FP4549, were used in combination with ten no-clean paste fluxes. The underfill was dispensed using two different dispense patterns. The assemblies were subjected to JEDEC level 3 moisture sensitivity testing followed by Liquid to Liquid Thermal Shock (LLTS) up to 2000 cycles.
After JEDEC level 3 testing, Kester TSF-6502, Kester TSF-6522, Almit BM1-RMA and Heraeus CL 84-7360 gave no bridges with FP4548. With the FP4549, all four Kester fluxes, Heraeus CL 84-7360, and Cobar 385 gave no solder bridges after the JEDEC test. In LLTS cycling, Heraeus CL 84-7360, Kester TSF-6502, Cobar 385, Almit BM1-RMA and Kester TSF-6522 gave the least number of extrusions with both underfills. Kester TSF-6502 gave no bridging until 2000 LLTS cycles with both underfills. Also the combinations of Kester TSF-6522 and Cobar 385 with FP4549 gave no bridging until 2000 LLTS cycles. With both underfills, Indium fluxes gave most extrusions and bridges.
Reliability Testing Of Two Dexter Encapsulants And Ten Fluxes
Authors: Nikhil Vichare and K. Srihari
Abstract: This report discusses thermal shock reliability testing of flip chip assemblies built with ten fluxes and underfilled with two Dexter underfills, FP4548 and FP4549. For each underfill, the effect of the flux and the fillet thickness on solder fatigue failures was investigated. Issues in fillet cracking and underfill delamination are discussed for both underfill materials. Dexter FP4548 gave slower solder fatigue, slower underfill delamination, and less fillet cracks than FP4549. In terms of solder fatigue, both underfills performed well with Heraeus CL 84-7360 and Kester 9611 fluxes. Neither underfill performed dramatically better or worse with any of the ten fluxes and the choice of flux could be based on other considerations.
Authors: Felix Bruno and K. Srihari
Abstract: Solder extrusion and bridging during thermal excursions are one of the many failure mechanisms observed for flip chip assemblies. During underfilling, voids may form near the solder joints. When the flip chip assemblies are subjected to peak reflow temperatures during JEDEC testing, solder can flow or extrude into the voids. These extrusions weaken the fatigue resistance of the solder joints. Extrusions that bridge two solder joints cause the package to fail because of the electrical short.
The substrate used in this experiment, pads defined by a trench solder mask opening, is the most challenging design to underfill without entrapping voids. Underfilling was made even more difficult by the very fine gap between the chip and solder mask, which ranged from 0.5 to 1.0 mil. Flip chips were built with 4 no-clean tacky fluxes and underfilled with 12 underfills. These assemblies were subjected to JEDEC Level 3 preconditioning followed by three reflow cycles. The assemblies were examined for extrusions and bridging after the JEDEC Level 3 test. Despite the obvious interactions between underfill and flux residue chemistries, 6 of the 12 underfills did not show a significant difference in extrusions between the four fluxes. The other 6 underfills gave either significantly more or fewer extrusions with a particular flux.
Jedec Level 3 Testing Of Underfill-Flux Combinations With A 240"C Peak Reflow Temperature
Authors: Felix Bruno and K. Srihari
Abstract: With the expected migration to lead-free solders, circuit boards and surface mount components will have to endure much hotter reflow temperatures. With peak reflow temperatures of as much as 260°C, components will have to be qualified at these temperatures with the JEDEC Level Moisture Sensitivity tests, and existing material sets may have to be modified. For flip chips, the choice of underfill and flux will directly affect whether these components will survive the hotter reflow temperatures. This experiment is part of a series of experiments to identify underfill-flux combinations that will pass JEDEC tests with lead-free reflow profiles.
In the present experiment, 23 underfills were tested in combination with 3 no-clean paste fluxes. The flip chip assemblies were subjected to JEDEC Level 3 with a 240°C peak reflow temperature. After the test, the assemblies were examined for underfill delamination and solder extrusions. The most noticeable trend was that underfills with short cure times (“snap cure”) most often gave underfill delamination failures. Of the 23 underfills, 18 passed with Heraeus TF38, 15 passed with Kester TSF-6502, and 11 passed with Indium FC-NC-LT-C. No parts failed electrically and most of the chips with underfill delamination had not completely delaminated (“popcorned”).
Solder extrusions are strongly affected by the substrate and chip layout as well as the underfill and flux choice. This substrate design, fine pitch pads defined by a trench mask opening is particularly challenging because underfill voids can form in the trenches between the solder joints. Nine underfills gave no solder extrusions with any flux and 16 underfills had no solder extrusion bridges with any flux.
Method Of Assessing Crack Growth In Epoxy Due To Hydrothermal Fatigue
Authors: H. G. Retsos, E. J. Kramer, M. Sivasambu and C.-Y. Hui
Abstract: Fatigue crack growth in the epoxy underfill of direct chip attach (DCA) microelectronic assemblies mounted onto printed circuit boards (PCB) due to thermal cycling, particularly in the presence of moisture, is a major mode of failure during reliability testing. Our objective is to develop a protocol for accelerated thermal fatigue testing that will allow us to predict the crack growth under milder service conditions for the realistic geometry of the assembly. To accomplish this task, we want to measure the growth per thermal cycle, da/dN, of a crack in a model epoxy underfill for various values of the range in strain energy release rate DG at the extremes of the thermal cycle. The initial experiments have used an Invar fixture in the form of a U with epoxy filling the space between the two metal arms with a pre-crack introduced from the open end along the long axis of the U. We periodically measure the growth of the crack from the pre-crack using optical microscopy after the Invar fixture has been transferred a certain number of times between a water bath at temperature Tup and a water bath at temperature Tl where Tup > Tl and both Tup and Tl are less than the glass transition temperature Tg of the epoxy. The crack growth da/dN per thermal cycle increases as roughly the third power of the thermal excursion parameter Dt º (Tup-Tl)(2Tg-Tup-Tl) and since DG depends linearly on Dt, our results suggest a power law of the form da/dN = A(DG)3
With this method, da/dN as small as 40 nm have been measured. Unfortunately, the design of the Invar fixture has a flaw that makes it much less than ideal for these experiments. While we initially assumed that the arms of the Invar U could be approximated as rigid and non-bending under the thermal stresses, finite element calculations show that for any reasonable thickness of the Invar arms, these arms bend like cantilever beams. This fixture geometry is also subject to adhesive failure of the Invar-epoxy interface. We have thus been designing a different specimen in which an outer ring of epoxy is allowed to shrink thermally onto a cylinder of Invar. A pre-crack is introduced from the outside of the ring along the radius. Using finite element modeling to determine the DG for this geometry, we should be able to make rapid progress over the next few months.
Characterization Of An Ltcc Flip Chip Ceramic Substrate
Authors: Ji Hyon Mun and K. Srihari
Abstract: A Low Temperature Co-Fired Ceramic (LTCC) flip chip carrier was characterized. The size and location of the chip pads were measured. For 800 pads on ten carriers, the average pad diameter was 4.28 mils with a standard deviation of 0.15 mils. As expected with this technology, greater random variations were observed in the pad locations than is typical with the photodefined processes. The variation from the average measured pad location was 0.55 mils with a standard deviation of 0.36 mils.
Substrate Characterization For Flip Chip On Flex
Authors: Felix Bruno and K.Srihari
Abstract: Two flexible circuits manufactured by Innovex and Nitto Denko were characterized to evaluate the variation in flip chip pad size and the dimensions of the openings in the photoimageable coverlay. The sizes of the copper features had standard deviations of 0.17 mil or less. Based on these statistics, the 3s range would be +/- 0.5 mil. Because of poor coverlay registration to the copper features, one large 252 mil by 260 mil coverlay opening is used to define the pads for each chip. The minimum/maximum range for the coverlay length and width was better for Innovex, 1.8 mil, compared to almost 4 mil for Nitto Denko.
Accelerated Testing Of Transfer Molded Flip Chips
Authors: Nikhil Vichare and K. Srihari
Flip chip assemblies were built with 3 no-clean paste fluxes, Heraeus TF38, Kester TSF-6502, and Kester 9611, and transfer molded by Dexter (Olean, NY). The transfer molded flip chips were subjected to JEDEC level 3 moisture sensitivity testing with a peak temperature of 240°C or higher. Despite an imperfect molding process that gave voids in the mold compound under the chip, only one of 19 parts popcorned during JEDEC testing. The parts were then tested in Liquid to Liquid Thermal Shock (LLTS). LLTS results were comparable with capillary flow underfills. The two mold compounds, did show a preference for the Kester 9611 flux. Chips built with that flux lasted more than 4000 cycles before the first failure.
Underfill Process Codification - 2001 Update
Authors: Antonio Prats, Peter Borgesen, Sandeep Tonapi, Pericles Kondos, Daniel Blass and K. Srihari
Abstract: The capillary flow-driven flip chip underfill process may be taken to include the selection of equipment (dispenser) and material. Creation of the process certainly involves specification of parameters such as bakeout requirements, substrate temperature, needle size, dispense paths (height above the substrate, distance to chip edge, length of pass), dispense rate, needle temperature, volume in each pass, timing of passes, cure parameters. Optimization of the process and specification of the process windows should minimize important variations and account for the inevitable variations (statistics and tolerances).
The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and troubleshooting. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.
The individual sections of this document are carefully organized to minimize the amount of experimental work actually required to reach your goals.
Study On Self-Filleting Of Underfill-Flux Combinations
Authors: Ji Hyon Mun, Felix Bruno, Antonio Prats and K. Srihari
Abstract: Self-filleting was studied in flip chip assemblies that were built with eleven underfills and four no-clean tacky fluxes. The effect of underfill-flux combination on self-filleting was studied, using an L-dispense pattern without a close-up pass and two dispensing volumes. Based on the fillet thickness measurements, self-filleting was classified into three categories: good self-filleting, self-filleting with scatter in the fillet thickness, and poor self-filleting. The source of scatter in the fillet thickness distribution was attributed to the effect of the flux.
Authors: Thomas Driscoll, Gary Lehmann and Eric Cotts
Abstract: The study of fluids is a subject that has generated investigations in a variety of academic disciplines and industrial applications. Particularly, the flow of complex fluids, both non-Newtonian fluids and filled suspensions, is becoming increasingly more prevalent in industry. The strong interest in nanotechnologies has generated an interest in the flow of these complex fluids into smaller and smaller geometries. The flow of industrial encapsulants and model suspensions of polystyrene microspheres in silicon oil were investigated in flow cells of different dimensions. The average flow distance measurements were calculated from the change in capacitance of the flow cell as the encapsulant/suspension displaced the air in the flow cell. Material properties of surface tension, static contact angle, and viscosity were measured for the purpose of modeling the flow of these materials. The wetting processes that drive the flow are characterized through calculations of the dynamic contact angle.
A modified version of the Washburn model, derived from the assumptions that the flow is characterized as a quasi-steady, isothermal, laminar flow of one fluid displacing another in a planar channel, was examined by comparison with the experimentally measured data. Within the model, the dynamic nature of the contact angle and the viscosity were accounted for. The model captured the general, qualitative behavior, of the flow quite well. The model also captured the quantitative variations with strain rate. Systematic differences between the model and experimental data were typically on the order of 10 – 15 %. The dynamic wetting characteristics of the flow were examined through the calculation of the dynamic contact angle. The dynamic contact angle was calculated using the modified model from the measured average flow front velocity. Comparison of the dependence of the angle on velocity to standard relations originally established for unfilled, Newtonian fluids showed that curves generated using the viscosity of the filled suspension, as opposed to the unfilled carrier fluid, provided better prediction of the wetting angle within the context of the Hoffman relation. The implication is that, while the fluid within 2 to 3 particle diameters of the contact line must be considered as unfilled, the region that characterizes the bulk material determines the contact angle, establishing a lower limit on the region that determines the contact angle during flow.
Effects Of Adhesive Properties On Optical Subassembly Deformation
Authors: S. Mahesh, C.Y. Hui and Peter Borgesen
The effect of thermal coefficient match on the alignment of optoelectronics packages are studied. In particular, we investigated the usage of adhesive in such packages. Finite element results show that minor variations in the wetting of the adhesive up the edges of the component can cause misalignment of the optical device. For the geometries studied in this work, we found that a thicker adhesive will lead to less warpage of the assembly and hence less misalignment. A simple analytical expression is derived for the warpage of an idealized optical bench. This expression allows us to quickly assess the effects of material properties and geometry on alignment.
Authors: Angela Quintanilla and K.Srihari
Abstract: Mechanical tests were performed to evaluate the strength of two photocurable adhesives that were cured in small gaps between solid surfaces. The adhesives considered in these experiments were AbleluxTM A4061T and AbleluxTM AA50T. The adhesive was manually dispensed in the gap between two syringe needles of different diameter and then subjected to various curing conditions, such as different light exposure time or thermal curing time. The strength of the cured adhesive was evaluated by pulling the needles with a steadily increasing force and recording the load at which the assembly broke up.
Automated Pin Transfer Studies Of Optical Adhesives
Authors: David Rae and K. Srihari
Abstract: Automated pin transfer studies were undertaken using industrial equipment to investigate material and process parameters for transferring optical adhesives. Using Ablestik AbleluxTM A4083T, and a model substrate, regular deposits of average weight approaching 1 mg were achieved. A number of parameters were studied to observe trends including nominal transfer height, withdrawal speed from the substrate, and withdrawal speed from the reservoir.
Authors: Angela Quintanilla and K.Srihari
Abstract: Experiments were carried out with two photocurable adhesives, AbleluxTM AA50T and AbleluxTM A4061T, in order to determine how the degree of cure was affected by the cure conditions. The degree of curing of samples that had been exposed to light and samples that had been thermally cured was evaluated through DSC (Differential Scanning Calorimeter) analysis. The effect of different ambient conditions, such as the presence of oxygen and nitrogen, on the degree of curing was also analyzed. In addition, DSC heat flow curves were used to determine the Tg of the adhesive AA50T.
Automated Pin Transfer Of Two Optical Adhesives
Author: Pericles A. Kondos
Abstract: Pin transfer experiments were performed with two optical adhesives of very different viscosities in a GPD dispenser slightly modified for this purpose. Several relevant parameters were tested and a methodology was developed for measuring the volume of the deposits. In this early stage the measurement method is still too time consuming but refinements are planned for future experiments. However, several qualitatively important observations were made.
Pin Transfer Of Optical Adhesives
Authors: Sunil Gopakumar and K. Srihari
Abstract: A preliminary investigation of the pin transfer of optical adhesives is described. Several methods are available for the transfer of adhesives, such as stencil printing, dispensing and pin transfer. However, the question arises as to the smallest amount of adhesive that could be accurately and repeatably transferred by any means. This research focused on manual pin transfer, as a method of transferring small amounts of adhesives for optoelectronics applications. A methodology was developed to accurately measure the volume of adhesive that was transferred. Since a manual process was adopted, variations were observed in the amount of adhesive that was transferred.
Effects Of Dynamic Wetting On Pin Transfer Of Optical Adhesives
Authors: Thomas Driscoll, Peter Borgesen and Eric Cotts
Abstract: Model studies were conducted to elucidate effects of dynamic wetting on an automated pin transfer process. Results could be rationalized in terms of competing physical mechanisms, and anticipated generic trends and scaling parameters to look out for in more realistic process development were discussed.
Effect Of Curing Parameters On The Ableluxtm A4083t Optical Adhesive In A "Realistic" Configuration
Authors: Sarang Kayande and K.Srihari
Abstract: Optoelectronics packaging often involves the use of adhesives in narrow gaps between rigid surfaces. The cure kinetics and resulting materials properties here may well be very different from those of the bulk materials. A ‘degree of cure,’ as determined, for example, by DSC does not reflect the performance issues of practical concern. A generic test vehicle representing a large group of optoelectronics products was used to investigate the sensitivity of the performance of the AbleluxTM A4083T optical adhesive to cure parameters. The present initial effort used adhesion as a measure of performance and maintained a fixed gap size of 5mil and a depth of 1mm.
Effect Of Curing Parameters On Ableluxtm 146t In A Small Gap
Authors: Sarang Kayande and K. Srihari
Abstract: A steel pin was inserted into a 1mm deep hole in an aluminum plate and the 5 mil wide gap between them was filled with the AbleluxTM 146T adhesive, which was then cured, by a combination of blue light and postcure at 100oC in air. The dependencies of shear strength on cure parameters were determined and results compared to those obtained for the A4083T adhesive.
Optiwork Compact C+L Wideband Polarization Insensitive Isolator Tear Down & Characterization
Authors: Peter Borgesen, Pericles Kondos, Antonio Prats and Lawrence Harvilchuck
Abstract: A polarization insensitive optical isolator effective over an extended wavelength range was disassembled in order to identify and characterize current ‘typical’ passive component assembly practices. A forthcoming report will discuss consequences and potential improvements.
Mechanical Testing Of Single Mode Optical Fibers Spliced By A Beginner
Authors: Kaustubh Nagarkar and K. Srihari
Abstract: The first 30 optical fibers spliced by a beginner after brief instructions were tested for mechanical reliability in dynamic tensile tests. Exercising great care, a surprisingly good mechanical quality was achieved.
Authors: Angela Quintanilla, Kaustubh Nagarkar and K. Srihari
‘Pristine’ optical fibers were tested in dynamic and static bending. Restrictions on short-term handling, say during packaging, were proposed. Otherwise, results were interpreted in terms of bending stresses and compared to tensile test data reported elsewhere.
On The Application Of Different Crack Growth Laws To The Analysis Of Optical Fiber Tests
Author: Peter Borgesen
Abstract: Three different proposed analytical forms of crack growth kinetics in optical fibers were considered. All three are based on the assumption that incremental crack growth at constant humidity varies with the stress intensity factor, KI. Parameters of the individual laws were determined by comparisons of predictions to experiments reported in the literature. An expression was derived, allowing the assessment of the largest initial defect in a fiber by a dynamic tensile test. The relative potential of each individual law for the extrapolation of an accelerated test result to ‘life-in-service’ was discussed. Analytical expressions were derived from each law for the life of a fiber under a static load.
Mechanical Testing Of Erbium Doped Fiber Splices
Authors: Kaustubh Nagarkar and K. Srihari
Abstract: Erbium doped fibers commonly have to be spliced to regular single mode fibers. Such splices were found to be mechanically weaker, and thus potentially less reliable, than splices between two single mode fibers. The mechanical quality as measured in dynamic tension was found to depend on the fiber types, the splicing recipe, and their interactions.
Effects Of Handling On The Strength Of Optical Fibers
Authors: Kaustubh Nagarkar and K. Srihari
Abstract: The extent of damage to optical fibers due to different handling procedures was evaluated. Optical fibers were either simply bent for certain periods of time or were handled severely to damage the coating with or without exposing the bare glass. The strength of the fibers was measured by exposing them to dynamic tensile tests.
The Effect Of Humidity On The Strength And Fatigue Of Optical Fibers
Author: Peter Borgesen
Abstract: Literature data and results of our own tensile and bending experiments were evaluated in an attempt to incorporate a humidity dependence into a crack growth law for optical fibers. While systematic trends appear and a procedure for organizing our test results is established further work is needed before we may extrapolate these to service conditions.
Effects Of Moisture & Stripping On Life & Strength Of Optical Fibers In Bending
Authors: Angela Quintanilla, Kaustubh Nagarkar and K. Srihari
Abstract: Effects of ambient humidity and drying in air or vacuum on the life of a ‘pristine’ (undamaged) single mode fiber in different degrees of static bending were determined. A simple dynamic bending test was used to assess the damage incurred in the individual steps of a mechanical stripping process.
Tensile Testing Of 'Pristine' Optical Fiber
Authors: Kaustubh Nagarkar and K. Srihari
Abstract: Optical fibers ‘as received’ from the manufacturer were tested in tension under a static load and under a linearly increasing load. The ultimate failure load in dynamic tension was seen to increase with loading rate and decrease with increasing ambient humidity. Using these results to determine the typical largest initial defect size the corresponding life under a given static load was predicted assuming different crack growth laws. Comparisons to experimental data helped in the identification of the preferred law to be used in future assessments of the consequences of specific handling and damage for ‘life in service’.
Sem Analysis Of The Origins Of Failure In Optical Fibers
Authors: Kaustubh Nagarkar, K. Srihari and Antonio Prats
Abstract: This report describes the preliminary studies on the fracture surfaces of optical fibers that failed in bending. Fibers were bent to different radii, and were kept under static bending until failure. The fracture surfaces were observed utilizing a Scanning Electron Microscope (SEM). The points from where the failures originated were determined and their deviation from the point of maximum stress on the surface of the fiber was measured. The analysis showed that the deviations seem to follow a normal distribution.
Effects Of Splicing Parameters On The Mechanical Strength Of Optical Fibers
Authors: Kaustubh Nagarkar and K. Srihari
Abstract: The effects of stripping, cleaning, splicing, and recoating on the tensile strength of single mode optical fibers were measured separately and together. The strength was strongly reduced relative to that of ‘pristine’ fibers, primarily due to damage in stripping.
Mechanical Testing Of Stripped Optical Fibers
Authors: Kaustubh Nagarkar and K. Srihari
Abstract: The effect of stripping on the strength of optical fibers was studied using tensile tests. The coating of the optical fibers was removed with different types of mechanical strippers and the extent of damage caused to the bare glass due to cleaning was also evaluated.
Optical Fiber Testing And Damage
Author: Peter Borgesen
Abstract: The present work offers an overview of our current understanding of crack growth in, and failure of, optical fibers under mechanical loads. Emphasis is placed on the potential for ‘invisible’ (not immediately obvious) damage in packaging and handling. Such damage should, of course, be assessed in terms of the consequences for optical functionality and ‘life in service’. An extreme sensitivity to load and, to a lesser extent, ambient humidity makes this strongly dependent on anticipated service conditions. Accelerated tests and recommended approaches to life prediction are discussed.
Attachment Processes With Eutectic Au80sn20 Solder
Author: Eric Cotts
Abstract: The present work reviews existing knowledge and understanding of the Au-Sn soldering metallurgy. Although initial confusions as to details of the phase diagram appear to have been resolved there is otherwise a paucity of data in the literature, particularly as far as reactions with contact metallizations are concerned.
Author: Pericles A. Kondos
Abstract: Pieces of gold and eutectic gold-tin solder were heated together under various conditions and for various lengths of time. The samples were afterwards inspected for soldering with optical microscopy and SEM. For samples heated inside a DSC, heat flow curves were also produced and studied. Several phenomena were qualitatively observed and recorded. Some quantitative analysis of the results was also attempted.
Optoelectronics Packaging Research 2001
Author: Peter Borgesen
Abstract: The present report offers an overview of our first year of optoelectronics packaging research within the Area Array Consortium. Activities included studies on assembly and design of actual products, Au-Sn soldering, numerous aspects of optical adhesive properties and use, and optical fiber handling and reliability. Important results are briefly described or reviewed, interpretations are updated where warranted, and attempts are made to put the individual pieces in the appropriate context.
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