1999 Reports

Assembly Of Chip Scale Packages On Microvia Interconnects: Part I

Authors: Parvez M.S. Patel and K. Srihari

Abstract: With the increasing interconnect density in semiconductor packaging and the use of area array packages such as Ball Grid Array (BGA) and Chip Scale Packages (CSPs), the standard electrical routing methods and design rules for Printed Circuit Boards (PCBs) are being challenged. The use of High Density Interconnects (HDIs), or microvias, fabricated by mechanical or non-mechanical means, is being adopted as an alternative to through-hole drilled vias in order to cope with the routing requirements. Different routing designs are being explored to meet the growing needs for these high density interconnects. The technique of via in pad, wherein the via pad is also used for component attachment, can be employed to further increase the CSP routing density associated with both micro and through-hole vias. The robustness of CSP assembly on organic PCBs with varying pad geometries is being investigated in a laboratory environment at Universal Instruments Corporation.

This report addresses the first of a series of experiments planned to investigate component assembly on high density PCBs. The assembly and reliability issues involved with different pad geometries (via-in-pad, partial via in pad and the dog-bone structure) are to be studied. An experiment that evaluated the self-centering properties of CSPs on different pad designs was also carried out. The results indicate that CSPs could fully self-center even with a placement offset of 75% of the pad diameter.

Assembly Of Wafer Level Chip Scale Packages On Microvia Interconnects - Build # 32

Authors: Parvez M.S. Patel and K. Srihari

Abstract: High Density Interconnects (HDIs), or microvias, fabricated by mechanical or non-mechanical means, are being adopted as an alternative to through-hole drilled vias in order to cope with increasing signal routing requirements. Different routing designs are being explored to meet the growing needs for these high density interconnects. The technique of via in pad, wherein the via pad is also used for component attachment, can be employed to further increase the routing density associated with both micro and through-hole vias for Chip Scale Packages (CSP).

This report outlines the assembly of a ‘wafer level’ CSP - Package "AE" - and the flex–based CSP - Package "N", on HDI boards using UIC Test Board 3 (UIC CSPTB-3). A total of 96 "AE" packages and 32 "N" packages were assembled on the test board with half of these assemblies built using flux and the other half by printing solder paste. These packages were assembled on non-solder mask defined pads and the via-in-pad patterns. All assemblies were found to be electrically good, but the via-in-pad assemblies showed the presence of voids causing concern with the reliability of the solder joints.

Assembly Of Chip Scale Packages On Microvia Interconnects: Part Ii

Authors: Parvez M.S. Patel and K. Srihari

Abstract: There is an increasing demand for reliable second level assemblies of area array packages on printed circuit boards that use High Density Interconnect (HDIs) routing techniques. Via-in-pad structures, where the via pad is also used for component attachment, is being increasingly employed to increase the routing density associated with both micro and through-hole vias for Chip Scale Packages (CSP) and Ball Grid Arrays (BGAs). A series of experiments (builds) were carried out to understand the assembly and reliability concerns associated with the second level interconnect on via-in-pad, dog bone and conventional pad structures.

This report outlines the assembly of a flex with elastomer CSP - Package "L", a rigid substrate with interposer - Package "F", and a flex BGA – Package "U" on the high density interconnects on UIC Test Board 3. A total of 60 "L" packages, 10 "F" packages, 10 "U" packages were assembled on the test boards. Half of these assemblies were built using flux and the other using solder paste. Two packages were found to electrically open after assembly. The via-in-pad joints also showed the presence of voids in the solder joints. The packages are currently undergoing thermal cycling to study the effect of the different assembly and design variables on their reliability. The reliability results are presented in a separate report.

Assembly To Study The Effect Of Ball Diameter On The Reliability Of Area Array Packages (Build #34)

Authors: Parvez M.S. Patel and K. Srihari

Abstract: Solder joint standoff is an important factor that influences the reliability of the package at the second level. With increasing standoffs, the reliability of the solder joint increases. The standoff can be increased by either decreasing the board pad area, having solder mask defined geometry in place of pad defined geometry, by increasing the volume of solder paste deposited, or by increasing the component’s bump diameter. By decreasing the board pad diameter, the allowable area for the solder bump to collapse decreases, thereby increasing the joint standoff. The main purpose of the experiment carried out using this build is to study the effect of increasing the component bump diameter and thus the solder joint standoff on the reliability of the assemblies.

Several packages were used in a specifically designed experiment to study the effect of the increase in bump diameter on the package reliability. These packages were similar in all respects to previously assembled packages, except for the increased bump diameters. Cross-sectional analysis and reliability studies were then carried out to study the effect of an increase in bump diameter on the solder joint reliability. During the experiments, a shift in the die location was observed on some of the assembled packages. These components have been documented and sent for reliability analysis. This would help relate the effect of die location on the solder joint crack initiation and propagation during thermal cycling.

Study Of Voids In The Via-In-Pad Solder Joint

Authors: Parvez M.S. Patel and K. Srihari

Abstract: High Density Interconnects (HDIs), or microvias, fabricated by mechanical or non-mechanical means, are being adopted as an alternative to through-hole drilled vias in order to cope with the increasing signal routing requirements of fine pitch, high I/O packages. The technique of via in pad, wherein the via pad is also used for component attachment, can be employed to further increase the routing density associated with both micro and through-hole vias for Chip Scale Packages (CSP).

It was found during the CSP/BGA assembly process development effort that the via-in-pad solder joint showed the presence of voids. Voids, approximately the size of the via opening, were seen at the openings of the vias or sometimes towards the component side. A set of experiments was conducted to study the origin of these voids and the factors that govern their formation. The entrapment of air in the via during the printing process was found to be the biggest contributor for void formation. Via geometry and pad surface finishes were the other factors affecting void formation. Different printing techniques were investigated to avoid the entrapment of air in the via. Finally possible methods to eliminate void formation in the via-in-pad joints are suggested. It was found that offset printing reduced voids by more than 90%. In addition, it was found that pre-applied solder in the form of Hot Air Solder Leveling (HASL) filled the vias at the attachment pads without causing voids. For printed paste applications, modifications of the stencil could be made to reduce void formation.

Solder Bumping For Ball Grid Arrays

Authors: Jeff Schake, Mohammad Yunus and K. Srihari

Abstract: Solder bumping is an important process step in the manufacturing of BGAs. In mainstream production, a highly robust solder bumping process is essential with requirements of rapid accurate deposition and uniform bump height distribution. Furthermore, this bumping process must be stable and produce high yields in order to support high reliability performance standards. Solder bumping of BGAs using different methods such as solder paste stencil printing and reflow, solder sphere attach with mini-stencil, and solder sphere stencil printing were studied. The bumping was performed for three reasons:

To investigate alternative ball attach process methods.

To facilitate building samples for evaluation of Pb-free solders (i.e. aging, shear testing, crack propagation, etc.).

To allow the completion of Flip-Chip/BGA devices to evaluate the assembly of 1st and 2nd level variables.

Techniques of printing solder paste and mini-stencil sphere placement did not produce desirable results. However, the method of sphere printing has achieved excellent yields with eutectic Sn/Pb and other Pb-free alloy systems. This report outlines the research effort towards the development of a robust solder bumping process.

Area Array Placement Yield Prediction

Authors: Manikandan Munikrishnan and K. Srihari

Abstract: The ability to predict the placement yield of an assembly process is very important for development of the process and to make strategic decisions regarding the materials and equipment required. The present report describes a Monte-Carlo simulation program, which predicts the number of defects occurring during placement of an area array device, based on user supplied statistics for in-plane substrate variations and machine accuracy. For the purposes of this program, defects are defined as the placement of the center of a solder bump on top of the solder mask or laminate without contacting the metal pad. The user has the option of including or excluding the case where a bump misses the top of a pad but makes contact with the side-wall. The present version of the program does not consider the proximity of other conductors and predicts yield only for a device with eutectic tin-lead solder bumps. The repeatability of the program has been tested and the range of total number of errors is equal to the square root of the total number of errors. This report is a user’s guide for the application and also discusses the assumptions made in the simulation model.

A Cost Comparison Of Csp With Alternate Packaging Technologies

Authors: Vinu Yamunan and K. Srihari

Abstract: Chip Scale Packaging has generated widespread interest in the electronics industry by virtue of the advantages it offers over existing technologies. Real estate savings, increased I/O density and superior electrical performance over the peripheral leaded devices are some of its qualities. Reliability, possible reworkability and robustness provide it an edge over Direct Chip Attach components. However, this is a relatively young technology and is therefore expensive. Other technologies like DCA can also be quite expensive because of the need for infrastructure, underfilling, slower throughput, and KGD issues, Etc.

The objective of this research is to develop a methodology that would assist a decision-maker with the economic justification for the use of CSP components in applications and products. The research methodology involves the comparison of the cost of assembling a board with one technology (such as QFP, BGA or DCA) with the cost of assembling a functionally equivalent board having CSPs. The values of the different cost facets are completely user defined. However, default values are also provided. The software model allows the user to save a set of input values from a run and reuse them, perhaps to perform sensitivity analyses on different facets of the cost. The metric used for the comparison is the assembly cost per board. The cost model has been developed using Microsoft Excel (Version 4.0).

Characterization Of Fcbga Test Board 4

Authors: Jaydutt Joshi and K. Srihari

Abstract: This report focuses on the characterization of the BGA ball side of the FCBGA Test Board – 4. The FCBGA Test Board – 4 was designed for various reasons such as lead-free ball attach process development, study of CTE on solder fatigue, warpage contribution of device on reliability, effect of the heat sink attach on the performance of a package, Lead-free solder paste evaluation. This report focuses on the characterization of the BGA ball side of FCBGA Test Board - 4 for use in the bumping process [Schake, 1999].

Surface Insulation Resistance And Z-Axis Dielectric Strength Testing

Authors: Jaydutt Joshi and K. Srihari

Abstract: This report presents the results of Surface Insulation Resistance (SIR) and Z- axis dielectric strength testing for high density interconnect substrates evaluated for the Area Array Consortium. Two test vehicles, namely CSP/DCA Test Board–3 (CSP/DCA TB-3) and Test Vehicle–2 (TV-2), were used and evaluated. Four vendors supplied CSP/DCA TB-3, which was manufactured using different technologies and materials. CSP/DCA TB-3 contained two patterns (4 and 8 mil pitch) for SIR evaluation. Patterns were evaluated with and without the application of flux for the degradation in SIR. Serpentine structures and Z-axis comb patterns were designed into CSP/DCA TB-3, to evaluate Z-axis dielectric strength. This test vehicle contained two Z-axis (10 and 20 mil pitch) test patterns. TV-2 was supplied by Vendor E for evaluating the degradation in SIR. It contained 6, 8 and 25 mil pitch SIR patterns. All the samples were exposed to temperature, humidity and bias conditions. For evaluation, the samples were exposed to 85o C, 85% RH and 48 V for 168 hours. It was found that dendrite formation on the patterns causes degradation in the SIR. It was observed that the SIR patterns for the photoimageable dielectric material exhibited the least Sir value as compared to the FR – 4.

Evaluation Of A High Density Microvia Test Board

Authors: Parvez M.S. Patel, Jaydutt Joshi and K. Srihari

Abstract: Trends in miniaturization and silicon integration have placed additional pressures on printed circuit board technology. Microvia technology and high density circuit boards with built up multilayers are being aggressively developed to address routing issues associated with the new area array devices such as Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), and Direct Chip Attach (DCA).

The CSP/DCA Test Board-3 has been designed specifically to study the reliability and assembly concerns related to microvia technology. Component sites have been designed using conventional pads, dog-bone, and via-in-pad routing to assess the properties of the solder joint and its reliability with respect to these pad structures. Currently, four vendors offering different via formation technologies have supplied the test board. The boards have been characterized in an effort to better understand the effect of different board parameters and anomalies on the final assembly and reliability of the packages. This report presents the results of the characterization performed on the CSP/DCA Test Board - 3. Pad diameters, via diameters, registration, mask openings, and other related offsets were measured at different locations on the board for the four vendors. Any noticeable defects or observations were documented in an effort to analyze any failures or reliability problems that arise.

Shadow-Moir" Processing Of Csptb-3 Samples

Authors: Mark S. Seus and James M. Pitarresi

Abstract: The study and understanding of thermally induced warpage in chip scale packages (CSPs), and their assemblies, is important to the development of this new technology. The thermal loading of an electronic assembly is a major concern during the reflow assembly process. If warpage of the component and/or substrate is excessive, the solder joint will bridge or gap, creating the need for component repair and/or replacement. Also, the shape of the solder joint will change due to this deformation causing concerns with the assembly's reliability. Through understanding and control of the warpage phenomenon, the performance of an assembly may be optimized.

Shadow-Moiré Interferometry is used to measure out-of-plane displacement (i.e., warpage) during a simulated reflow cycle. Two trends emerge as a result of an analysis of the warpage data. Sample thickness and thermal gradient appear to directly affect warpage behavior. All of the boards examined had a stack-up that was symmetric; however, sample 4 is substantially thicker than the other coupons. It was the only sample to demonstrate a flat surface for any significant time period during the test, and it had warpage magnitudes that were consistently low as compared with the others. The warpage data also showed that the highest thermal gradients (i.e., during ramp-up and ramp-down) produced the highest warpage magnitudes in every case. It is recommended that additional studies be directed toward a complete understanding of this phenomenon.

Via Reliability Evaluation And Failure Analysis (Phase I)

Authors: Jaydutt Joshi and K. Srihari

Abstract: Reliability of fine structure vias in high density boards was evaluated in this research. Presented are the results of the reliability evaluation and failure analysis performed on microvia interconnect structures designed as a part of the CSP/DCA Test Board-3 (CSP/DCA TB-3) and Test Vehicle-2 (TV-2). The reliability of the microvia interconnect structures has been evaluated using Liquid-To-Liquid Thermal Shock (LLTS) testing. The microvias were fabricated using different laser ablation technologies and glass reinforced dielectric material. The technologies evaluated were YAG laser drilling and YAG-CO2 laser drilling. Initial cross sections were made to evaluate the vias and parameters such as wall inclination, shape, and plating thickness. Resistance of the via chain was measured before LLTS testing and periodically thereafter, at intervals of 100 LLTS cycles. Samples that failed were subjected to non-destructive and destructive analysis in order to fully understand the failure mechanism. In general the microvia structures lasted for 2000 LLTS cycles. There was a via diameter size related separation of the data. In general, the larger vias (8 mils) had mean fatigue lifetime of 5% higher than the small vias (3 mils). Failure based on manufacturing defects such as incomplete fiber bundle removal made up the bulk of early failures found in testing.

Via Reliability Evaluation And Failure Analysis (Phase Ii)

Authors: Jaydutt Joshi and K. Srihari

Abstract: The results of the reliability evaluation and failure analysis performed on microvia interconnect structures designed as a part of the CSP/DCA Test Board-3 (CSP/DCA TB-3) in Phase II are presented in this report. The reliability of the microvia interconnect structures was evaluated using Liquid-To-Liquid Thermal Shock (LLTS) testing. The microvias were fabricated using different laser ablation and photoablation technologies. Non-glass reinforced and glass reinforced dielectric materials were used. Laser technologies such as YAG laser drilling and YAG-CO2 laser drilling were evaluated. Samples for testing were provided by four vendors. Initial cross sections were made to evaluate the vias and parameters such as wall inclination, shape, and plating thickness. Resistance of the via chain was measured at various stages of LLTS testing. Samples that failed were subjected to non-destructive and destructive analysis in order to fully understand the failure mechanism.

Component Characterization Report

Authors: Anthony Primavera and Sanjay Sharma

Abstract: Under the CSP/DCA consortium many different packages were evaluated for issues such as construction methods, material properties, manufacturing defects, metrology and package reliability. These several samples represent a wide range of package both in the CSP and BGA type. Some of the important features of the samples evaluated include pitch size, array type, construction and ball size. The samples had a bump pitch between 0.5mm to 1.27 mm in an area, perimeter and depopulated array. The number of I/O's varied from 6 to 412 and package size ranged between 100 to 1000 mils with an overall package thickness of 28 to 70 mils. The packages have bump height varying from 7 to 24 mils and bump diameter of 12 to 30 mils. The carrier material of the packages include flex, laminate, ceramic, flex with elastomer, and silicon. Sample package types varied from live, daisy chain and mechanical samples.

This report consists of a description of the package construction details as observed from package cross section, the statistical variation observed on the bump diameter, height, pad size, bump location and pitch. Also included are the results of a warpage study done at both room temperature and elevated temperature. Results are presented for the component level reliability study, such as moisture sensitivity, exposure to high temperature and high temperature aging test. Details on the individual packages are given in the appendices.

Warpage Measurements Of Selected Area Array Packages

Authors: Madan Mohan Sitaraman and K. Srihari

Abstract: As a part of the component characterization effort in the Area Array Consortium, a large sample of different packages are evaluated with respect to their metrology. This report presents the results of efforts that have addressed component warpage determination. The techniques and the procedure used for the determination of component warpage at room temperature and reflow temperature are described.

The results of the warpage measured at Robotic Vision Systems Inc. (RVSI) were compared with those obtained from a laser profilometer and Shadow-Moiré interferometery for a selected number of components. Although it was observed that the results obtained from the laser profilometer and the Shadow-Moiré interferometer were slightly different from those obtained from RVSI, the change of warpage, before and after reflow correlated for the two methodologies. Also, the warpage at reflow was measured for all three package types using Shadow-Moiré interferometry.

"Preliminary Characterization Of Package ""Af"", A Wafer Level Chip Scale Package"

Authors: Madan Mohan Sitaraman and K. Srihari

Abstract: This preliminary report outlines the characterization of Package "AF", which is a wafer-level Chip Scale Package (CSP). The construction, dimensions and key features of the component are discussed and details obtained from cross-sections are provided. Measurements such as the bump height, bump diameter and coplanarity were done on a fixed sample size using a WYKO surface profiler, a Coordinate Measurement Machine (CMM) and the results obtained are provided in this report. Also, a sample of 10 components was subjected to high temperature storage to determine the effect of aging on the package characteristics. The physical features of the aged samples are compared with the non-aged samples and some representative cross-sections are analyzed.

An Overview Of Wafer-Level Chip Scale Packages

Authors: Madan Mohan Sitaraman and K. Srihari

Abstract: Chip Scale Packages (CSPs) are rapidly becoming an important element in electronics manufacturing because of their small size, performance and cost advantages. The semiconductor wafer paradigm – package an entire wafer at one time, not just a single die – offers the promise of miniaturization and high performance, without higher costs. This paradigm is commonly known as wafer-level packaging and CSPs of this type are known as Wafer-Level CSPs. The advantage of the wafer-level CSP stems from the fact that it can be packaged directly on the wafer during the wafer processing stage rather than after dicing. Additionally, the Integrated Circuits (ICs) can be burned-in and tested before being diced into individual, fully-finished packages yielding additional cost savings. Currently, there are more than a dozen wafer-level CSPs available in the market. Some of the well-known wafer-level CSPs have been listed in this overview report along with their basic constructional features, types, and their manufacturing process. Some issues in the assembly of wafer-level CSPs on to a board are discussed in the final section.

Overview Of Csp Warpage Issues

Authors: Robert Fenton and James M. Pitarresi

Abstract: The study and understanding of thermally induced deformations in chip scale packages (CSP) is important to the development of this technology. The understanding of warpage is important for the characterization of electronic components. The thermal loading of the component is a major concern during the reflow assembly process. If warpage is excessive, the solder joint will bridge or gap, creating the need for component repair or replacement. Also, the shape of the solder joint will change due to this deformation causing concerns with the component’s reliability. Through control of the warpage phenomenon, the performance of a component may be optimized. The method of warpage characterization and the associated measurement techniques are discussed.

In this study:

Many techniques have shown to be viable for out-of-plane measurements of CSP’s. While the extensive theory of some techniques (such as the Shadow-Moiré interferometer or the laser-based surface profilometer) attribute to high resolution, the simplicity of others (such as the mechanical probe or the coordinate measurement machine) is attractive for quick and easy measurements. With all the techniques available for measurements, component warpage is able to be measured accurately.

Comparison of the measurements available has shown that room temperature warpage is captured by a number of techniques including a mechanical probe, a coordinate measurement machine, a laser-based surface profilometer, and the Shadow-Moiré interferometer.

Of the techniques available, only the Shadow-Moiré interferometer is currently able to perform measurements at an elevated temperature. Given that all of the other measurements are within a reasonable tolerance of the measurements taken by the Shadow-Moiré interferometer, it is concluded that correct warpage values are extracted from Shadow-Moiré at elevated temperatures.

The work with finite element modeling has predicted the out-of-plane contours as per the techniques outlined above for some of the components. Also, through the use of finite element modeling and warpage measurements, the estimation of unknown material properties is possible.

Board Design Module - A User's Manual

Authors: Manikandan Munikrishnan and K. Srihari

Abstract: Substrate design is constrained by a variety of factors such as the minimum spacing required between traces and the number of layers required to route out the bumps. It should also address a variety of concerns that affect yield and reliability. A decision support system for substrate design would be a very important tool for board designers. A beta version of such an application - the "Board Design Module" - has been developed. This module provides the framework for the decision support system and incorporates some basic design rules. This report is a user's guide for the application and describes the functionality, inputs and outputs of the software.

A Database Of Area Array Components

Authors: G.S.Nathan and K. Srihari

Abstract: The constructional features of any package widely influence the board design and assembly yields in the electronics assembly. This report discusses a software tool that serves as a knowledge base of constructional details of the area array components that have been characterized in the consortium effort. This software helps the design and process engineers to decide on a specific component construction to package the die. This report also serves as a user's manual for the application – ‘Component Browser’. It describes the installation procedure and the operational details of this software.

1999 Chip Scale Package Program Complete Summary

Author: Anthony A. Primavera

Abstract: Current standard surface mount devices such as peripheral leaded packages and area array devices offer robust assembly yields and good long term solder joint reliability. New devices and packaging methods must compare to or perform better than standard devices in assembly and reliability arenas in order to gain acceptance and wide use. In an attempt to achieve the functionality and density of bare die assembly, a new family of devices has been developed by the packaging industry which are very close to the dimensions of the bare silicon die. Chip Scale Packages (CSP) are defined as devices only slightly larger than the die. These devices satisfy the demands of miniaturization while retaining the advantages of conventional packages. CSPs have been assembled using conventional surface mount techniques and the long-term solder joint reliability has been assessed for over 30 different components. While the 1999 CSP program is a continuation of previous Consortia activities, the focus was on fine pitch devices and PCB technology. 1999 Efforts Focused on Several Key Areas including:

Components

High Density PCB Technology

Assembly of Fine Pitch CSP

Codification of Information

Materials Evaluation

Rework of Fine Pitch

Reliability

This report is a final overview and summary of the 1999 Calendar Year CSP half of the Consortium. A complete process, materials and reliability summary is presented. Further information about each topic is available in supporting documents and reports, which are referenced in this report.

Overview Of A Generic Flip Chip Plastic Ball Grid Array (Fcpbga) Package

Authors: Paresh S.Limaye and James M.Pitarresi

Abstract: A generic Flip Chip Plastic Ball Grid Array package (FCPBGA) is currently being developed by the Area Array Consortium at SMT Laboratory, Universal Instruments Corporation. In this package, a global coefficient of thermal expansion (CTE) mismatch is generated between the PCB and the FCPBGA package by making the die almost as large as the substrate. This package shows a great promise as a test package for studying different assembly, board and substrate parameters as well as different solder alloys. The assembly process of the FCPBGA package involves bumping of a FR-4 substrate followed by dispensing of an encapsulant on the substrate. This is followed by the placement of a glass slide (in place of the actual Si die) on the substrate and finally the encapsulant is cured. The report discusses some of the issues involved with the package i.e. warpage of the substrate and moisture sensitivity. Also some of the possible experimental applications of this package are discussed.

Estimation Of Warpage Of A Multi-Layered Substrate: A User's Manual

Authors: Manikandan Munikrishnan and K. Srihari

Abstract: The ability to predict the warpage of a multi-layered, high-density substrate has numerous implications on the design and material selection of the substrate. This report describes the software tool that has been developed to estimate the effective lamina properties and warpage of a multi-layered substrate. The application calculates the warpage using Plate Theory Equations based on the material properties input by the user. This report also serves as a user's guide for the application.

Reflow Profile Development For Lead - Free Solders

Authors: Mohammad Yunus and K. Srihari

Abstract: Tin/Lead (Sn/Pb) solders have been extensively used in the electronics industry as an interconnecting material. Environmental concerns of lead-based soldering have prompted an increase in the research activities trying to identify a "drop in" replacement for lead-bearing solder alloys. Several concerns, including material and process issues, need to be addressed before a suitable alloy is chosen. Among the processes, reflow soldering is extremely critical as the solder joint is formed during this phase of assembly. Many lead-free solders have a higher melting point than eutectic Sn/Pb. This necessitates the examination of metallurgical and physical changes that components and PCBs may undergo during a higher peak temperature reflow. In addition, the multiphase alloys being considered do not have single melting solidification point, thus affecting the phase formation during the cool down from liquidous. The issues and concerns that relate to the reflow process have to be completely understood. This report discusses the reflow profiles generated for four different lead-free solders. An attempt has been made to study some of the issues pertaining to lead-free soldering in this initial study directed at deriving a better understanding of the necessary requirements for lead-free soldering.

Shear Strength Of Lead-Free Solder Alloys

Authors: Mohammad Yunus and K. Srihari

Abstract: Eutectic Sn/Pb solder has been widely used as a soldering material in the electronics industry, but it has been documented that there are environmental and toxicity issues associated with lead based alloys. The electronics industry has been forced to look for an alternate soldering alloy. An initial study was conducted to study the mechanical strength of lead-free solder joints. The work reported here examines the shear strength of two lead-free alloys on standard pad metallurgies such as Cu OSP, Ni/Au, Ni/Pd and compares their performance against the standard eutectic Sn/Pb alloy.

The effect of isothermal aging of the solder joint on shear strength was also evaluated. The effect of pad geometry such as pad defined and solder mask defined, was also evaluated. The intermetallic growth for the lead-free alloys under evaluation was characterized to correlate with the mechanical strength. Shear strength was evaluated by shear testing using an Instron Materials Tester and the maximum load and displacement at maximum load data was analyzed to provide insight into the mechanical strength of solder joints. The results indicated that the failure mechanism was ductile and there were no indication of brittle failure even after isothermal aging at 125° C. After 500 hours of aging, there appeared to be a transition to brittle failure mode, but there were no indication of a complete brittle failure even after aging for 1000 hours. The shear strength of lead-free alloys were comparable to eutectic Sn/Pb alloy.

Solderability Evaluation Of Components Bumped With Lead-Free Alloys

Authors: Mohammad Yunus and K. Srihari

Abstract: Environmental concerns of lead-based soldering have prompted the move towards identifying a suitable lead-free alternative. A lead-free system would not only consist of soldering material that is lead-free, but also component terminations and Printed Circuit Board (PCB) surface finishes that are also lead-free. This warrants the use of lead-free solder bumps on area array components. Research has been focused on defining the relative solderability performance of lead-free bumped components with that of eutectic Tin/Lead (Sn/Pb) alloy. The lead-free alloys investigated did not reveal any solderability issues for the various test conditions. However, the components bumped with the Sn/Pb alloy indicated some solderability issues after 48 hours of baking at 150° C. This report discusses the testing methodology adopted and the results observed.

Wetting Ability Of Lead-Free Solder Alloys

Authors: Mohammad Yunus and K. Srihari

Abstract: The electronics industry is being pushed towards eliminating lead from its products. This has stimulated an increased interest in alternatives to traditional eutectic Sn/Pb solders. In an attempt to set a baseline for further studies in lead-free alloys, an initial study was conducted to study the wetting abilities of a few lead-free solder alloys. The work reported here examines the wetting ability of a few promising lead-free solder alternatives on Cu OSP, Ni/Au and Ni/Pd pad metallurgies. The effect of multiple reflow on the wetting ability and the effect of flux on the wetting ability were also investigated. Although this is not a comprehensive evaluation of all the factors, the results give us some valuable insight into the wetting ability of lead-free alloys. Solder wettability was determined by performing an area of spread test, by measuring the diameter of spread and characterizing the wetting ability based on the wetting angles. The results indicated poor wetting performance of lead-free alloys on CuOSP pad metallurgy; however their performance was comparable to eutectic Sn/pb solder on Ni/Au and Ni/Pd pad metallurgy. No significant effect of multiple reflow cycles was observed on the ability of lead-free solders. It is important to note that this preliminary study is to be repeated as materials are developed for lead-free. The fluxes used in today’s commercially available solder paste are based on Sn/Pb alloys and will most likely need to be reformulated for the more stringent requirements of lead-free systems.

Delamination Of Die And Encapsulant In Flip Chip Packages

Author: James M. Pitarresi

Abstract: This report addresses the delamination of die and encapsulant in flip chip packages. A simple 3D finite element model was built to study the delamination. Considering delamination to be a local effect, only a part of the package was modeled, with solder joints not included in the analysis. The model consisted of only die, encapsulant and substrate materials. The material properties used were linear-elastic and temperature-dependent. The predicted path of delamination was in reasonable correlation with the observed results.

Parameter Study Of A Flip-Chip Bga Package

Author: James M. Pitarresi

Abstract: A finite element based parameter study of key variables affecting solder joint reliability for flip-chip BGA packages is presented. In general, it was found that changes in the overmold or underfill have a negligible impact on the second level solder joints. For the first level joint life, modest changes in substrate materials, overmold geometry, and overmold thickness above the die were negligible. Increasing the die gap did produce a small decrease in the joint life, as did increasing the die thickness. It was noted that, above 10 mils, an increase in die thickness produced a negligible change in the joint life. Increasing the underfill modulus lead to a small increase in the joint life while increasing the CTE produced a modest decrease in joint life. The most significant factor influencing the first level joint life was the presence of underfill material under the die. When some material is present under the die a significant increase in joint life is realized compared with no material under the die.

Reliability Modeling Of Chip Scale Packages

Authors: James M. Pitarresi, Sundar Sethuraman and Bala Nandagopal

Abstract: A finite element based approach for estimating the thermal cycling reliability for chip scale packages is presented. The methodology is based on Anand’s viscoplastic constitutive law for the solder response and Darveaux’s crack growth-rate model for solder fatigue. A Weibull two-parameter failure distribution is assumed. Three-dimensional finite element models were built for each of the twenty-three packages studied. The number of cycles to fifty percent package reliability was estimated for two different thermal profiles (0oC to 100oC, 20 minute; -40oC to 125oC, 60 minute). Good correlation between the measured and predicted life was observed for many of the packages that have completed their testing. Each of the package’s measured life was typically within the expected plus/minus 1.5X error band of the method. A small number of parameter studies were performed using the three-dimensional models. It was observed that increasing the flexibility of the elastomer layer in flex-based devices resulted in a higher joint life while a larger via size and decreased die thickness both produced a modest joint life increase.

Effect Of Solder Voids On Reliability Of Chip Scale Packages

Authors: James M. Pitarresi and Sundar Sethuraman

Abstract: A finite element based approach to study the effects of solder voids on reliability of chip scale packages (CSP) is presented. Three different void sizes were analyzed. Considering the fact that the corner joints are usually the highly stressed joints, the void was modeled on those joints. A twenty-minute 0oC to 100oC thermal cycle was used as loading for the analysis. It was found that for a package with bigger voids, there was a significant decrease in life compared to that of a package without any void. However, the smaller voids had negligible effect on the package life.

Moir" Processing Of Component Samples

Authors: Mark S. Seus and James M. Pitarresi

Abstract: This report summarizes measurements conducted to determine coefficient of thermal expansion (CTE) for a variety of chip scale package (CSP) families. A total of forty-eight samples, from sixteen package families, were analyzed. Moiré interferometry was used as the basis of the measurement technique. A number of grating transfer techniques were developed and examined in an effort to identify the most effective method for use with CSPs. The most satisfactory process involved the transfer of the grating at 60oC and CTE evaluation at room temperature. The CTE analyses were performed on the bottom surface for thirteen of the sixteen part families analyzed. For the remaining three families, edge transfers were used to avoid problems associated with incomplete transfers due to warpage.

CTE values had an average value of 8.48 PPM/oC and standard deviation of 3.91 PPM/ oC for the entire group of parts. Components with flex as a carrier tended to have low CTE values, while packages containing flex with elastomer demonstrated high CTE values. Standard deviation values (for individual component types) ranged from 0.34 to 6.62 PPM/oC, although the majority of values were in the range between 0.91 and 3.38 PPM/oC.

Csp Warpage Characterization Using Shadow-Moir" Interferometry

Authors: Mark S. Seus and James M. Pitarresi

This report summarizes the warpage measurements during a simulated reflow cycle for a variety of electronic components. A total of ninety-six samples, from twenty-four different package types, were analyzed. The goal was to identify the magnitude and shape of warpage throughout the reflow cycle. Observations were of the shape and magnitude of the samples' warpage at three points throughout the heating cycle: 1) initially at room temperature (also referred to as initial warpage), 2) at peak temperature (also referred to as peak warpage), and 3) at return to room temperature following reflow (also referred to as final warpage). The initial warpage refers to the average of initial warpage values for all of the samples of a package type (the same is true for the peak and final warpage). The average warpage is a single metric intended to give a rough idea of the warpage magnitude for each package type. This number is an average of the initial, peak and final warpage magnitudes for all samples of a given package type.

From the measurements, three trends were identified. A relationship was identified between the size of the package and the overall warpage. The overall warpage tends to decrease as the package size decreases. The second trend was identified when the data was sorted by the difference between the peak and final warpage. Sorted in a descending fashion (also referred to as "descending delta value" in the report), it appears that components demonstrating high initial warpage magnitudes tend to have larger differences between peak and final warpage magnitudes. Finally, it was found that as the die size to package size ratio decreases the average warpage and the initial warpage increase. It is hypothesized that as the region of the comparatively stiffer die decreases relative to the substrate, the substrate has additional freedom to deform.

Warpage Modeling And Measurement

Authors: Robert Fenton, Anthony Primavera and James M. Pitarresi

Abstract: Smaller size and high performance demands have driven the consumer electronics industry away from large through-hole devices and toward space saving surface mount technology (SMT). Within the SMT arena, Ball Grid Array (BGA) components have emerged at the forefront replacing Quad Flat Packages (QFP) and Thin Small Outline Packages (TSOP). As the price of circuit board real estate increases, the need for yet smaller components has driven SMT. While Direct Chip Attach (DCA) is at the top of the space-saving technology, the reliability and initially high assembly cost has led to the development of a smaller family of BGA’s known as Chip Scale Packages (CSP). A CSP is a BGA that has a package-to-die dimension ratio of less than 1.2. [1] This technology offers the electrical performance of DCA with the reliability of a BGA.

The study and understanding of thermally induced deformations in CSP’s is important to the development of this technology. Warpage modeling and measurement is used for the characterization of out-of-plane displacements, or warpage, in electronic components. The thermal loading of the component is a major concern during the reflow assembly process. If warpage is excessive, the solder joints will bridge or gap, creating the need for component repair or replacement. Also, the shape of the solder joint will change due to this deformation causing concerns with the component’s reliability. Through control of the warpage phenomenon, the performance of a component may be optimized. The method of warpage modeling and the associated measurement techniques are discussed.

Effect Of Voids On The Reliability Of Solder Joints: Part I

Authors: Mohammad Yunus and K. Srihari

Abstract: Voids in solder joints have been considered as a defect in electronics assembly. The factors that affect void formation are complex and involve the interaction of may other factors. There are no established standards for void size and void area in a solder joint for it to be deemed defective. Inspection criteria have been very subjective. The effect of voids on the reliability of solder joint may depend not only on the size, but also on frequency and location. This study is focussed on investigating the effect of voids on the mechanical robustness of the solder joint. The size, location and frequency effects on the reliability were studied. Testing was done by a mechanical deflection testing (Torsion) system. Failures were analyzed for the failure modes by cross sectional analysis. The results indicate that voids, which are greater than 50 % of the solder joint area, decrease the mechanical robustness of the solder joints. Small voids also have an effect on the reliability, but it is dependent on the void frequency and location. Additionally, voids often coincide with microvia in pad assemblies, in which there is an entrapment of air in the via during the assembly process. These voids are typically the diameter of the microvia and have shown to have reduced the mechanical robustness of the joint in many cases. Of course the void size, location and frequency will dictate the degree to which the "mechanical" integrity is reduced. This report covers the mechanical aspects of voids/reliability. A separate report [Yunus & Srihari, 1999] examines the thermal fatigue properties of solder joints containing voids. A thermal-mechanical (by FEM) evaluation of the effect of voids in area array solder joints has been performed by [Pittaressi, et al., 1999] finite element modeling.

Study Of Solder Joint Embrittlement For Nickel Gold Pad Finish (I)

Authors: Paresh S.Limaye and James M.Pitarresi

Abstract: Solder joints assembled on Nickel-Gold pad finishes have been known to exhibit a brittle behavior in shear testing after aging. To date speculative reasons for the problem have been suggested in literature however no conclusive reason has been assigned as to the root cause of this embrittlement phenomenon. Most literature points to a ternary Ni/Sn/Au intermetallic [Cotts et al, 1999] [Mei, Z. et al, 1998].

In this investigation, nickel-gold plated boards from twenty-eight vendors were investigated with regard to the solder joint embrittlement phenomenon. The goal was to find the board parameter(s) needed to predict the defect in a given board as well as survey the PCB industry for the occurrence of the phenomena. Initially, solder joint shear testing was carried out to see if any trends could be observed with respect to the mechanical properties of the joint, however no such trends were observed. It was also found that nickel and gold plating thickness did not show any significant correlation to the occurrence of brittle failure.

SEM analysis revealed that all the brittle samples analyzed showed very rough and uneven intermetallic layers and nickel, tin and gold were observed to be present on the surface. However, SEM analysis of the ductile samples revealed smooth and uniform intermetallic layers with presence of only nickel and tin. This indicates that the amount of gold tin intermetallic located at the pad/ball interface in the ductile joint is relatively insignificant when compared to a brittle joint. Also all the brittle failures observed before aging were attributed to improper fluxing and poor solderability of the pads. The SEM analysis has been carried out on a limited number of samples and more work needs to be done. A second round of testing is proposed in which all the boards tested will have solder mask defined pads. This will reduce the amount of erroneous data present due to pad rip-offs from the board as the solder mask holds the pad in place and only the solder joint is sheared.

Effect Of The Proximity Of Pths To Microvias On The Reliability Of Microvia Structures

Authors: Jaydutt Joshi and K. Srihari

Abstract: The results of the reliability evaluation and failure analysis performed on via test structures placed in close proximity to PTHs designed as a part of the CSP/DCA Test Board-3 (CSP/DCA TB-3) are presented in this report. The reliability of the microvia interconnect structures was evaluated using Liquid-To-Liquid Thermal Shock (LLTS) testing. Microvias were fabricated using different build up technologies including non-glass reinforced and glass reinforced dielectric materials. Laser technologies such as YAG laser drilling and YAG-CO2 laser drilling were evaluated along with photodefined microvias. Samples for testing were provided by four vendors. Initial cross sections were made to evaluate the vias and parameters such as via wall inclination, shape, and plating thickness. The effect of proximity of microvias to the PTHs on the fatigue life was studied. The samples were tested for 2000 LLTS cycles. Testing revealed that vias located close to PTHs (<30 mils) showed fewer fails than those at a distance of greater than 30 mils. It is suspected that the local CTE effect of the PTH prevents microvias from debonding. The main failure mode of microvias is from the separation of the via plating from the underlying copper layer. It is speculated that the PTH keeps the microvia from separating. Therefore, microvias close to PTHs will last longer than those located farther away. These results were compared to bare board via reliability test results. Testing showed that vias (< 4 mils) failed earlier than greater diameter vias (6 mils and 8 mils). Plating quality of large (6 mils and 8 mils) vias was found to be better than smaller microvias (< 4 mils). Improper plating at the bottom of the via coupled with the high stress concentration resulted in a break at the via pad interface. The uncleaned epoxy and glass fibers in the via hole are a major cause of the via failure.

Reliability Testing Results For Chip Scale Packages: Phase Ii

Authors: Michael Meilunas

Abstract: A chip scale package (CSP) is a device that typically has a package to die dimension ratio of less than 1.2 (i.e. the package is less than 20% larger than the die). Also, the definition of a CSP has been such that it includes area array components with lead pitch of 1.0mm or less. Universal Instruments was involved in the reliability testing of CSPs with an emphasis on second level reliability. The failure mechanism of primary concern is solder fatigue damage that results from the inherent differential thermal expansion between the component and printed circuit board (PCB). In this research, air to air accelerated thermal cycling was used to evaluate package reliability. Factors investigated include PCB characteristics such as thickness, surface finish and pad size; assembly conditions including the reflow atmosphere, fluxing agent (paste or flux); double-sided simulations; voided packages and reworked components. Package characteristics were also tested and included: die dimensions, package size, substrate materials and mask opening dimensions. Testing was conducted at several sites under various conditions to include 0 to 100ºC, -40 to 125ºC, -40 to 100ºC and -55 to 125ºC cycles. The purpose of this project was to identify the dominant factors affecting CSP reliability and the modes of failure these factors invoke.

Reliability Testing Results For Chip Scale Packages

Authors: Robert Fenton and Michael Meilunas

Abstract: A chip scale package (CSP) is a device that typically has a package to die dimension ratio of less than 1.2 (i.e. the package is <20% larger than the die). Also, the definition of a CSP has been such that it includes area array components with lead pitch of 1.0mm or less. Universal Instruments was involved in the reliability testing of CSPs with an emphasis on second level reliability. The failure mechanism of primary concern is solder fatigue damage that results from the inherent differential thermal expansion between the component and printed circuit board (PCB). In this research, air to air accelerated thermal cycling was used to evaluate package reliability. Factors investigated include PCB characteristics such as thickness, surface finish and pad size; assembly conditions including the reflow atmosphere, fluxing agent (paste or flux) and double sided simulations. Package characteristics were also tested and included: die dimensions, package size, substrate materials and mask opening dimensions. Testing was conducted at several sites under various conditions to include 0 to 100ºC, -40 to 125ºC, -40 to 100ºC and -55 to 125ºC cycles. The purpose of this project was to identify the dominant factors affecting CSP reliability and the modes of failure these factors invoke.

Effect Of Voids On The Reliability Of Solder Joints

Authors: Mohammad Yunus and K. Srihari

Abstract: Voids in solder joints have been considered as a defect in electronics assembly. The factors that affect void formation are complex and involve the interaction of many other factors. There are no established standards for void size and void area in a solder joint for it to be deemed defective. Inspection criteria have been very subjective. The effect of voids on the reliability of solder joint may depend not only on the size, but also on frequency and location. This study is focussed on investigating the effect of voids on the reliability of solder joints. The size, location and frequency effects on the reliability were studied. Testing was done by mechanical deflection testing (Torsion) system and Air to Air Thermal Cycling ( -40°C/125° C). Failures were analyzed for the failure modes by cross sectional analysis. The results indicate that voids reduce the life of the solder joint. Voids which are greater than 50 % of the solder joint area, decrease the mechanical robustness of the solder joints. Small voids also have an effect on the reliability, but it is dependent on the void frequency and location. Additionally, voids often coincide with microvia in pad assemblies, in which there is an entrapment of air in the via during the assembly process. These voids are typically the diameter of the microvia and have shown to have reduced the mechanical robustness of the joint in many cases. Of course the void size, location and frequency will dictate the degree to which the "mechanical" integrity is reduced. This report covers the effect of voids on the reliability (mechanical robustness and thermal-mechanical) of solder joint. Additionally, a thermal-mechanical (by FEM) evaluation of the effect of voids in area array solder joints has been performed by [Pittaressi, et al., 1999] finite element modeling.

Rework Of Chip Scale Packages - Site Redressing

Authors: Ashish Alawani, Parvez M. S. Patel, Madan Mohan Sitaraman and K. Srihari

Abstract: Once a Chip Scale Package (CSP) is removed in a rework process, the site must be cleaned in preparation for a new package. The goal is to effectively remove the residual solder without damaging the solder mask material and/or lifting the pads. Currently, two methods are commonly used for the removal of residual solder. They either use a vacuum de-soldering system or a soldering iron with a solder wick. These are manual site-cleaning methods. An automated site cleaning system called the "scavenging system" is provided on the rework system used in this research effort. The aim of this study was to establish a comparison between the different site redressing options and to address the issues in the redressing of fine pitch CSPs. In addition to this, the scavenging tool, provided in the rework station used in this research effort, was characterized and subsequently compared to the conventional method of cleaning the site with a solder wick.

Rework Of Chip Scale Packages - Component Removal Process

Authors: Parvez M.S. Patel, Madan Mohan Sitaraman and K. Srihari

Abstract: Chip Scale Package (CSP) technology offers robust packages with a small footprint and high interconnect density. However, one drawback to CSPs and also to Ball Grid Arrays (BGAs) is the difficulty in the rework process compared to peripheral leaded surface mount devices or through-hole components. This difficulty is mainly due to the solder joints being hidden under the component body. The four main steps in the rework of any area array component are component removal, site redressing, solder replenishment/fluxing, and component replacement. Careful thermal profile development, rigorous process control, and proper equipment selection can greatly improve the CSP rework process.

Component removal involves non-destructively removing the damaged component by heating the solder to a temperature above its liquidus. In this process, some of the major concerns are: obtaining a proper thermal profile to avoid warpage, minimizing component/board damage, and avoiding damage to the adjacent components.

The aim of this study was to develop profiles and to establish a robust removal process that can be generalized for reworking CSPs, particularly for fine pitch (as low as 0.5 mm pitch) CSPs, keeping in mind the process variables and available resources.

Rework Of Chip Scale Packages - Component Replacement Process

Authors: Parvez M.S. Patel, Madan Mohan Sitaraman and K. Srihari

Abstract: After the defective Chip Scale Package (CSP) has been successfully removed, site redressing, solder/flux replenishment, and component replacement, follow. The site redressing operation removes most of the residual solder left on the reworked site, providing a coplanar solderable surface. Subsequent solder/flux replenishment process provides the necessary solder required for a solder joint that is electrically and mechanically sound. The component replacement process follows. It is the most important step in determining the reliability and yield of the rework process.

The aim of this study was: to evaluate different solder replenishment processes, to develop profiles that can be used for replacement, and to establish a robust replacement process. Some results obtained were:

For pitch sizes more than 0.75 mm, mini-stencil printing was found to be a simple and fast method of solder deposition involving minimal cost. For pitch sizes less than 0.75 mm, flux application is more practical than solder paste application.

Manual dispensing is extremely difficult since it was found to be difficult to dispense precise amounts of solder paste for fine pitch CSPs.

The temperature profile that can be used for component removal as well as replacement was successfully developed.

Higher standoff, approximately 1.5 to 2 mils more was observed for samples that used solder paste for replacement, than those using flux.

The use of a nitrogen atmosphere reduces the occurrence of solder balling, reduces the flux residues, and minimizes the oxidation of solder during reflow.

Lower airflow rates are needed for fine pitch (less than 0.75 mm) components to avoid shifting of the component during replacement.

Process Development For Rework Of 0.5-Mm Pitch Chip Scale Packages

Authors: Madan Mohan Sitaraman and K. Srihari

Abstract: With the advent of Chip Scale Packages (CSPs), the electronics manufacturing industry is faced with several challenges in the rework environment. Some of the challenges include the small size of the component and the solder ball, fine pitch of the components, small pad size, and a high number of I/Os. Another challenge is the board thickness, which is often 20 mils or below. This report discusses the rework of a 0.5 mm CSP. A generic process for the rework of fine pitch (less than 0.75 mm pitch) packages was developed. A set of assemblies has been reworked and is presently undergoing reliability evaluation. Various issues such as profiling, component removal, site redressing, fluxing, and replacement are discussed in detail. Multiple inspection methodologies are described and recommendations for successful rework are provided.

Characterization Of The Rework Machine

Authors: Madan Mohan Sitaraman and Gagan Batra

Abstract: An attempt to characterize the new rework system and develop heating profiles for components (Package "W", Package "V", and Package "G") on 62 and 31-mil thick boards (Test Board-2) for rework and repair has been made. The requirements for carrying out rework are first defined based on which the system behavior is analyzed and a certain procedure is established to carry out rework for any component-board combination. Once the system was characterized the profile development for removal and replacement was pursued for specific component-board combinations. Finally, the profiles developed were used for actual component removal and replacement. The removed and replaced components were then inspected based on the standards that such components must meet. The profiles were modified to improve the component removal and replacement process.

The system was made repeatable by cold starting, which involves heating it to a temperature and maintaining it for 2-3 minutes. An additional factor of size of board is taken into consideration. For large boards an additional process step is added to preheat the board to one temperature before actually starting the removal/replacement process cycle. The profiles for component removal and replacement are used for checking the repeatability of the system.

Process Overview: Rework Of Chip Scale Packages

Authors: Parvez M.S. Patel and K. Srihari

Abstract: Explosive growth of high-density packaging is having a tremendous impact on the electronic assembly and manufacturing industry. Ball Grid Arrays (BGA), Chip Scale Packages (CSP), and flip chip technologies are some of the most valuable elements of this emerging trend. The ability to rework these components is a key to their successful implementation.

The goal of the rework operation is to replace defective or outdated parts and create assemblies that are as reliable as the non-reworked assemblies. A generic rework process for BGAs, m BGAs and CSPs was developed in the research effort discussed in this report. This comprehensive effort involved systematic experiments to characterize the rework system and heating criteria adopted and develop robust component removal, site redressing, and component replacement processes. The process and material parameters that affect the individual steps and influence the success of fine pitch area array rework and solder joint robustness are discussed. BGAs and CSPs were reworked using the rework process developed and the solder joint reliability was assessed using accelerated thermal cycle testing and mechanical testing. Detailed reports on individual operations involved have been documented and the entire process overview has been presented in the following report.

Reliability Of Reworked Area Array Packages

Authors: Parvez M.S. Patel and K. Srihari

Abstract: The aim of any rework operation is to obtain assemblies that have reliability as good as, if not better, than the non-reworked assemblies. An entire rework process for the rework of Chip Scale Packages (CSPs) was developed at the Surface Mount Technology Laboratory at Universal Instruments Corporation. This involved the following steps: component removal, site redressing, solder replenishment, and component replacement. To validate the rework process developed, a set of assemblies were reworked using the defined process. The next step was to evaluate their reliability and compare the results with non- reworked assemblies.

This report explains in brief the various testing methodologies that are used to evaluate the reliability of surface mount assemblies. Various factors affecting reliability are discussed. The results of the reliability testing of reworked samples are also presented. It was found, at 95% confidence level, that the reliability of the reworked samples was comparable to the non-reworked assemblies.

Effect Of Time Between Bake Out And Assembly With Kester 9101 Reflow Encapsulant

Authors: Daniel L. Blass and Pericles Kondos

Abstract: Flip chip assemblies were built with Kester 9101 to study the effect of exposing the dried substrate to moisture before reflow encapsulant assembly. The substrate dryness requirements for reflow encapsulants are likely to be more stringent than for conventional underfills because of the higher processing temperatures in reflow. Indeed, underfill voiding increased after a dry board was exposed to 30°C/60%R.H. for just one hour before dispense and assembly. Soldering was not affected. Based on these results, a board must be used shortly after removal from dry storage or routed to drying. Board drying may be an important consideration in the implementation of flip chip with reflow encapsulants.

Effect Of No-Pb Bump Metallurgy On Flip Chip Underfill Delamination

Authors: Sandeep Tonapi and K. Srihari

Abstract: The assembly of flip chip with no-Pb solder bumps almost invariably involves higher reflow temperatures, as well as different compositions of the flux residues and perhaps different amounts of residue and a different adhesion of the underfill to the solder joint surfaces. The present work offered preliminary results on the effects of flux thickness, peak reflow temperature and solder bump metallurgy on the delamination of two underfill materials, the Namics U8437-3 and the Shin Etsu 5126. The metallurgy was found to affect delamination quite significantly.

Reflow Encapsulants: Assembly Issues And Processes

Author: Pericles A. Kondos

Abstract: A large number of reflow encapsulants from several suppliers were used in assemblies with different die and board types, and the results were tested for quality of soldering and voids after reflow. Other parameters that were varied were the encapsulant dispense pattern, board preparation, component placement force and holding time, and reflow conditions.

It was seen that bubbles always formed during encapsulant dispensing and die placement, but often the final result was void-free, partly at least due to bubble dissolution, which was helped by holding the assembly for a while at "soaking" temperatures in the neighborhood of 150° C. Board drying requirements appeared to be stricter than in the case of regular underfills. Even after prolonged drying and careful handling of the boards, voids were occasionally seen in the final product. Some materials, like the Questech and one experimental Kester, always produced voids. Others, like the Kester 9101 and the Dexter, usually led to no voids at all.

Die floating and movement after placement can be avoided by holding the die in place for sufficiently long time, allowing the material to wet the sides of the die.

Good soldering was consistently achieved by several encapsulants when the proper combination of holding time, placement force, and reflow conditions was used. Materials that don’t require postcuring seemed to be less tolerant of variations in the reflow profile.

Substrate Characterization And Placement Yield Prediction For A 4 Mil Pitch Flip Chip Assembly - A Case Study

Authors: Manikandan Munikrishnan and K. Srihari

Abstract: Overall flip chip assembly yields are affected by a multitude of parameters. The hope is that contributions from placement related defects may be kept negligible in this context. This is, however, often more a matter of the substrate tolerances than the placement machine accuracy. A case study was conducted on the 4 mil pitch flip chip on the Universal Test Board 3. Substrates were found to be in reasonable agreement with stated tolerances for the individual parameters. Some of these tolerances could be improved considerably by compensating for systematic over-etching of the metal lines and pads in design or by feedback to the supplier. Sensitivity studies were conducted using our "Area Array Placement Yield Prediction" program. Not surprisingly, even the most optimistic assumptions in terms of self alignment did not lead to acceptable yields for this pitch and substrate technology.

Area Array Assembly Yield Prediction Software User Manual

Authors: G.S.Nathan and K. Srihari

Abstract: This manual presents an overview of the features of the Assembly Yield Prediction program. It describes the installation procedure and the operational details of this software. The inputs of the program include the distributions of bump heights, board parameters and warpage. The assembly yield is calculated and estimated in terms in terms of parts per million defects. This software has been designed for the Windows 9x platform.

Effects Of Die Thickness And Substrate Rigidity On Die Cracking In Flip Chip Assemblies

Authors: Mukul Joshi and K. Srihari

Abstract: The risk of cracking an underfilled flip chip during handling or thermal excursions depends on, among other, the thicknesses (rigidities) of die and substrate. An additional dependence on die size is readily understood in terms of the increased chance of a critical defect. A total of 219 die of three different types were underfilled on various of five different FR-4 substrates and tested in Liquid-to-Liquid-Thermal-Shock (LLTS). Different modes of cracking were observed. Only one of the largest, 27 mil thick, die cracked on 62 mil thick substrates. A rather large number of smaller, 26 mil thick, die cracked but only on thinner (18-26 mil) substrates. Finally, only one out 87 small, 14 mil thick, die cracked (on a 20 mil thick substrate).

Effects Of Die Thickness And Wafer Dicing Parameters On Flip Chip Die Cracking

Authors: Andrew Giamis and Michael E. Scholz

Abstract: Die cracking is commonly observed when flip chips on thin FR-4 are tested in liquid thermal shock. This experiment investigated whether other factors such as die thickness and dicing parameters affected die cracking. Die thickness had a major effect on cracking for step-cut die with thinner die cracking much less in liquid shock. More data is needed to confirm this trend for single-cut die. For both single-cut and step-cut die, intermediate cutting speeds were found to be best when vertical die cracking was common. Single-cut and step-cut die often performed differently but there was not a consistent trend.

Flip Chip Reliability

Author: Daniel L. Blass

Abstract: This report provides an overview of the flip chip reliability efforts of the 1999 Area Array Consortium. It covers our understanding of the various failure mechanisms that cause the solder joints to electrically fail. The three most common failure modes are delamination enhanced solder fatigue, corner delamination caused by fillet cracking, and solder extrusion bridging. The various mechanical and chemical dependencies that affect reliability are also discussed.

Flip Chip Research In 1999

Author: Peter Borgesen

Abstract: Ongoing research within the Area Array Consortium addresses issues relevant to flip chip assembly onto organic substrates, whether for component manufacturing or Direct Chip Attach. These include chip and substrate layout, assembly and underfill processes, lid and heat sink attach, handling and effects of ambient exposure and thermal cycling. A major emphasis is on ‘codification’, i.e. on providing directly useful tools and guidelines for practitioners in the field. The following pages offer a status report as of the end of 1999.

Issues In Stencil Design And Print Experiments Using Conductive Adhesives

Authors: V. Muthiah and K. Srihari

Abstract: Electrically conductive adhesives are currently being considered as possible alternatives to solder. The present report describes part of the work aimed at optimizing the print process for the so-called Polymer Flip Chip (PFC) approach. The application to an 8 mil pitch perimeter array assembly was investigated and the feasibility of extending the approach to finer pitches assessed. Two different stencil thicknesses and a range of apertures were evaluated. A designed experiment was conducted to evaluate the effect of print pressure and print speed on the adhesive deposit.

Stencil Printing Of Electrically Conductive Adhesive At 6 Mil Pitch

Authors: Sakethraman Mahalingam, Muthiah Venkateswaran and K. Srihari

Abstract: The potential for extending one of the Polymer Flip Chip (PFC) approaches to pitches down to 6 mil was investigated. Previous work showed the achievable conductive adhesive deposits on die and FR-4 substrates with an 8 mil pitch. The only remaining question was whether similar deposits could be achieved on a 6 mil pitch without bridging.

Comparison Of Solder Extrusions In Liquid Thermal Shock And Air Cycling

Authors: Kevin J. Teed and K. Srihari

Abstract: The negative effects of solder extrusions on the electrical reliability of flipchip assemblies are of considerable concern for the establishment of a robust manufacturing process. During underfill, voids in the encapsulant can form near the solder joints. Solder from the joint can extrude into these voids during thermal cycling of the assemblies. These extrusions have the potential to bridge the space between neighboring joints. The identification of an attractive underfill material that minimizes the occurrence of solder extrusions would be of obvious interest.

4 different encapsulants were investigated in terms of their sensitivity to solder extrusions. For this purpose oxide-passivated flipchip assemblies were underfilled and cured. After cure the assemblies were cycled in either Liquid-to-Liquid-Thermal-Shock or Air-to-Air-Thermal-Cycling and the encapsulants were compared to each other terms of the number of occurrences of solder extrusions. The overall best performance was achieved for the Kester 9203.

Liquid Shock Testing Of Kester 9101 Reflow Encapsulant In 5 Mil Pitch Assemblies With Depopulated Corners

Authors: Viraj Patwardhan and K. Srihari

Abstract: The Kester 9101 reflow encapsulant was used to assemble 5 mil pitch die on 62 mil thick FR-4 substrates. Fillet cracking and underfill delamination from the die corners was the primary cause of electrical failure. The depopulated die corners delayed electrical failure until the corner delamination reached the solder joints. As in experiments with regular underfills, the single-row die failed earlier than the double-row die. Here, this may be partly due to bridging of the double-row die solder joints during assembly.

The 5 mil pitch die performed differently in liquid shock than the Edge-6 die. The Edge-6 die gave similar fillet cracking with the Kester 9101 but did not, however, give corner delamination with the Edge-6 die. The Edge-6 also failed sooner than the 5 mil pitch die despite the absence of corner delamination. The corner bumps tended to fail first for the Edge-6 die. The reason for the different performance of the Edge-6 and 5 mil pitch die has not been determined.

Liquid Thermal Shock Testing Of 6 Reflow Encapsulants In A 6 Mil Pitch Flip Chip Assembly

Authors: Viraj Patwardhan and K. Srihari

Abstract: Six reflow encapsulants were used to build 6 mil pitch flip chip assemblies on 40 mil thick FR-4 substrates. The assemblies were tested in Liquid-to-Liquid Thermal Shock (LLTS). Four encapsulants survived more than 1000 LLTS cycles before the first electrical failure, Dexter Hysol CNB837-44 (since commercialized as FluxFill 2000), Emerson & Cuming Amicon E1330, Questech P-Bond EF-7, and the Kester Se-Cure 9101. With reliability testing in progress, the Kester Se-Cure 9101 has reached 1500 LLTS cycles with no electrical failures thus far.

The 5 encapsulants that have completed testing showed similar failure modes in LLTS testing. The fillets cracked and delaminated from the edges of the chip. This led to delamination under the die that originated at the die corners. The corner delamination caused corner solder joints to fail. Later onset of corner delamination corresponded to later electrical failure. Considering the failure mode, it is possible that process or material formulation changes may lead to improved reliability.

Air Thermal Cycling Of Very Fine Pitch Flip Chip Assemblies Built With Kester 9101 Reflow Encapsulant

Authors: Viraj Patwardhan, V. Muthiah and K. Srihari

Abstract: Two fine pitch flip chip assemblies were built with the Kester 9101 reflow encapsulant using 4 and 5 mil pitch perimeter array die. The assemblies were tested in two accelerated air thermal cycles, Air-to-Air Thermal Shock (AATS) from -40° C to 125oC and Air-to-Air Thermal Cycling (AATC) from 0° C to 100oC.

The two assemblies performed in a similar manner in AATS but differently in AATC. The 5 mil pitch assemblies lasted nearly twice as long as the 4 mil pitch assemblies in AATC. This result is attributed to the two mechanical differences in the two assemblies, the gap under the chip, and the substrate thickness. As the performance in AATC was assembly specific, acceleration factors between tests would also be assembly specific. The acceleration factor from AATS to AATC was roughly 3.8 for the 5 mil pitch assemblies but only about 1.5 for the 4 mil pitch assemblies.

Some fillet cracking and solder extrusions were observed in AATC but not to the extent often seen with liquid thermal shock. Little delamination was observed in AATC. Despite the lack of delamination, the solder joints fatigued and failed. The location of failed solder joints could be determined in the 4 mil pitch assemblies and was found to occur near the die corners first.

Fully curing Kester 9101 in a second reflow was investigated as an alternative assembly process. This was not only an acceptable variation but it actually improved reliability over the regular post-reflow cure step of 30 minutes at 150° C.

Evaluation Of Shell Cariversetm Thermally Reversible Network Polymer As A Flip Chip Underfill

Author: Andrew Giamis

Abstract: Shell Chemical’s CARIVERSETM is a network polymer that features a thermally reversible covalent crosslinking. This unique feature could be used to create a thermally reworkable flip chip underfill. Reliability testing however found the present formulation to be too brittle. Mild air cycling of CARIVERSE underfilled flip chips caused the fillets to crack and even fall off. Similar cracking and delamination was observed under the chip and electrical failures occurred in just a few hundred cycles. If the CARIVERSE can be reformulated to improve the fracture toughness without loss of thermal reversibility, the material may be further investigated. Process issues such as the extremely high underfilling temperatures and slow capillary flow also pose significant challenges.

Liquid To Liquid Thermal Shock Testing Of 13 Encapsulants

Authors: Mukul Joshi and K. Srihari

Abstract: 13 encapsulants were tested for delamination from a small nitride passivated die on a 26 mil thick FR-4 substrate. The results were dominated by delamination originating from around the individual solder bumps, rather than from a die edge or corner. Both the performance of the individual materials and their relative ranking are likely to vary with standoff, flux, solder mask, and laminate. However, in a first screening for relatively robust materials three materials showed most promise: The U8437-2 and U8437–3 from Namics and the Kester 9203. All the experimental results with the statistical analysis, the observations and the conclusions are presented in the present report.

Thermal Shock Testing Of 4 Mil Pitch Assemblies With Very Thick Encapsulant Fillets

Authors: Viraj Patwardhan and K. Srihari

Abstract: Encapsulant fillet cracking at a die corner usually allows delamination to progress from there along the die passivation to the solder joints. As regards reliability, this is much worse than delamination originating from around the joints. It is speculated that the inevitable drop in encapsulant wetting at the sharp die corners and resulting reduction in fillet thickness there might affect fillet cracking at those locations. An experiment was therefore conducted, attempting to produce a more uniform fillet thickness.

A 4 mil pitch die was assembled onto a 62 mil thick FR-4 substrate and the 0.3 mil gap underfilled with 4 different encapsulants. The dispense volume was chosen so as to create very thick fillets. The assemblies were tested in Liquid-to-Liquid-Thermal-Shock (LLTS) and monitored for delamination and electrical failure. In general, the reliability was dominated by fillet cracking and corner delamination. Three of the encapsulants allowed 90% or more electrical failures by 1000 LLTS cycles. The fourth encapsulant, Johnson Matthey 8802, had a much better reliability. This encapsulant exhibited crack initiation much later and slow crack growth after that. This was attributed to a slight filler particle settling in the fillet, an effect that has been observed with other underfills. The first electrical failure occurred at 2000 cycles and 63% had failed by 3500 cycles. All of these failures appeared to be caused by corner delamination. The low incidence of fillet cracking is attributed to a slight filler particle settling in the fillet.

Effect Of Fillet Thickness On Delamination And Electrical Failures In 5 Mil Pitch Flip Chip Assemblies

Authors: Sandeep Tonapi and K. Srihari

Abstract: The effect of fillet thickness on delamination and electrical failures in 128 and 130 micron pitch flip chip assemblies in Liquid to Liquid Thermal Shock (LLTS) was studied. An earlier study showed thick encapsulant fillets in similar assemblies to crack at the corners of the die, leading to corner delamination and electrical failure. In the present work fillet thickness in the order of 6-10 mil were seen to delay or eliminate fillet cracking and enhance the assembly life. In the absence of fillet cracking, failure was related to delamination starting around the solder joints.

Different Thermal Shock Response Of Single And Double Row 5 Mil Pitch Flip Chip Assemblies: Effect Of Gap Size Or Substrate Variations"

Authors: Sandeep Tonapi and K. Srihari

Abstract: Recent research showed unexplained differences between 130mm pitch single perimeter row and 128mm pitch double row flip chip assemblies in Liquid-to-Liquid-Thermal-Shock (LLTS). An increased encapsulant delamination originating from around the larger number of solder joints in the latter assemblies was readily understandable. However, a clearly reduced tendency for the corner fillets to crack and allow for delamination from there was not. It was speculated that the differences might somehow be related to minor differences in standoff, substrate morphologies or (perhaps) local substrate rigidities. A model experiment has therefore been conducted in which these differences were carefully eliminated. The trend was found to still persist.

Underfilling And Liquid To Liquid Thermal Shock Testing Of 128 And 130 Micron Pitch Flip Chip Assemblies

Authors: Sandeep Tonapi and K. Srihari

Abstract: 5 mil pitch single and double row flip chip assemblies were underfilled and tested in Liquid to Liquid Thermal Shock (LLTS). This involved initial screening of 11 encapsulants to identify the two that would fill the 1.25 - 2 mil gaps under the die without voiding. These (Nagase Ciba 690/R3310 and Dexter EH0544) were then tested in shock between -55 ° C and 125 ° C. Failures appeared to vary with die site as well as with die type. Delamination of the encapsulant from the chip passivation progressed significantly faster for the single row die than for the double row die. This was true for both the encapsulants. Failures of the single row assemblies occurred by encapsulant fillet cracking at or near the corner of the die, leading to delamination from that corner and electrical failure as soon as the delamination reached the first solder joint. Corner fillet cracking was also observed for double row assemblies, although not as often. However, this did not always lead to corner delamination, and usually electrical failure occurred by solder fatigue crack growth initiating as encapsulant delamination started around the solder joints.

Liquid To Liquid Thermal Shock Testing Of The Kester 9101 Reflow Encapsulant

Authors: Viraj Patwardhan and K. Srihari

Abstract: 275 x 275 mil2 organic passivated die were assembled onto 62 mil thick FR-4 substrates using the Kester 9101 reflow encapsulant and tested in Liquid to Liquid Thermal Shock between –55oC and 125oC. Electrical failure was caused by solder fatigue crack growth presumably initiated by the delamination of the encapsulant from the solder joint surfaces. Failure may have been affected by encapsulant fillet cracking although this did not lead to delamination originating from the die edges or corners. Life times ranged between 1200 and 2200 cycles at which time encapsulant delamination from the die passivation was often not yet detectable. The results were not very sensitive to moderate variations in the reflow profile, nor were they improved by increasing substrate bake out and post cure times. For some reason a 4-up version of the same die was found to survive almost 50% longer at 50% assembly failure.

Liquid To Liquid Thermal Shock Testing Of The Emerson & Cuming E1330 Reflow Encapsulant

Authors: Viraj Patwardhan and K. Srihari

Abstract: 6 mil pitch perimeter array, nitride passivated flip chips were reflow soldered to 62 mil thick FR-4 substrates and tested in Liquid-to-Liquid Thermal Shock (LLTS), between –55oC and 125oC. First failure was observed after 1150 cycles and 50% failure occurred by about 1800 cycles. Unlike what was observed with the Kester 9101 reflow encapsulant, which used another die with organic passivation, electrical failures appeared to correlate with corner delamination. Once delamination began at a corner, it progressed at a relatively rapid rate and failure occurred when it reached a solder joint. This delamination was preceded by large cracks at the corners.

Process Development And Reliability Evaluation Of Polymer Flip Chip Assemblies

Authors: V. Muthiah and K. Srihari

Abstract: Electrically conductive adhesive technology is emerging as a potential replacement for lead based soldering. This report presents a compilation of work that has been conducted on conductive adhesives. The focus of this research was the evaluation of the potential use of the thermoset isotropic Polymer Flip Chip (PFC) material as a replacement for solder.

This research was performed in three phases. The feasibility of using conductive paste for flip chip assembly was evaluated, followed by print experiments and stencil design changes aimed at improving the yield. Three different curing conditions were tried and their effect on reliability was evaluated. These assemblies were subjected to air-to air thermal cycling, moisture exposure and liquid to liquid thermal shock testing. This report discusses the different issues in process development as well as the different reliability results.

Reliability Of Polymer Flip Chip Assemblies Evaluated Using Liquid-To-Liquid Thermal Shock

Authors: Sakethraman Mahalingam, Muthiah Venkateswaran and K. Srihari

Abstract: The reliability of Polymer Flip Chip (PFC) assemblies was assessed using Liquid-to-Liquid Thermal Shock (LLTS) between –55oC and 125oC. The die, bumped with conductive adhesives, was attached onto 62 mil thick FR-4 substrates with a thermosetting isotropic conductive adhesive, H20-PFE. Two different curing times were used; a vendor-specified time of 1.5 hours and a Differential Scanning Calorimetry (DSC) based time of 20 minutes. The samples were then underfilled and then subjected to a temperature of 30oC at 60% relative humidity for 9 days. Finally, the samples were tested in LLTS. The failure mode was classical corner delamination leading to failure of the corner joints. The joints failed at the bump-paste interface, possibly because the conductive adhesive is a thermosetting resin and the joint is formed after the conductive adhesive bumps on the die are cured.

Effects Of Board Bake On Underfill Delamination And Fillet Cracking

Authors: Kevin J. Teed and K. Srihari

Abstract: The potential for negative effects of moisture on the cure of the flip chip underfill is of considerable concern for the establishment of a robust manufacturing process. A need to bake and a limited time allowable between this and underfilling has obvious consequences for the process flow. So far, a conservative recommendation has been to require a 2-hour bake at 125oC of any board or assembly which has been exposed to ambient humidity for a total of 8 hours or more. The identification of an attractive underfill material, which would allow the expansion of this window, would be of obvious interest.

7 different encapsulants were investigated in terms of their sensitivity to moisture in cure. For this purpose oxide passivated flip chip assemblies were underfilled with and without pre-exposure to a 30oC/60%R.H. environment for 96 hours. After cure the assemblies were cycled in Liquid-to-Liquid-Thermal-Shock and the encapsulants compared to each other and to FP4511 in terms of corner fillet cracking and delamination from around the solder joints. The overall best performance was achieved for the Ablestik 443-6 and, if exposed to moisture, the Emerson & Cuming LA-4345-58.

Comparison Of 5 Underfills In Liquid To Liquid Thermal Shock

Authors: Sakethraman Mahalingam, Muthiah Venkateswaran and K. Srihari

Abstract: The 3310 and the 3002EX from Nagase Ciba, the U8437-3 from Namics, the Ablestik 7811, and the Johnson Matthey 8802 flip chip underfill materials were compared in both perimeter and area array assemblies using Liquid-to-Liquid-Thermal-Shock after a JEDEC Level III popcorn test. The area array assemblies had all solder joints at least 65 mil from the nearest die edge, eliminating any effects of the encapsulant edge fillets. The materials showed very different levels of sensitivity to the solder joint layout. However, the Namics material ensured the best performance of both types of assembly.

Effects Of Thermal History On The Strength Of Sn-Ag-Cu-In Flip Chip Solder Joints

Authors: Viraj Patwardhan and K. Srihari

Abstract: Reflow encapsulants are an alternative to the conventional underfill process. A volume of encapsulant is dispensed on the die site, the component is placed on the site and reflow soldered. The reflow encapsulant acts as both the flux and the underfill. The reliability tests performed on a set of assemblies built using two reflow encapsulants are discussed in this report, namely the Emerson & Cuming E54-4 and the Kester Se-Cure 9101.

When subjected to Liquid-to-Liquid Thermal Shock (LLTS), extensive fillet cracking was observed with the Emerson & Cuming E54-4 encapsulant in the early stages of cycling. This encapsulant also did not solder well and all assemblies were electrically failed by 77 LLTS cycles. Kester 9101 exhibited fillet cracking later in the thermal cycling. The first Kester 9101 encapsulated die failed electrically by 500 LLTS cycles and over sixty percent had failed by 1000 cycles.

Reliability Of Nokia Assemblies With Reflow Encapsulants In Liquid To Liquid Thermal Shock

Authors: Sandeep Tonapi and K. Srihari

Abstract: Recent work has demonstrated some of the difficulties in controlling the thickness of the encapsulant edge fillets. The development of a robust, automated underfill process thus requires among other the quantification of the acceptable range of fillet thickness for a given assembly. The present work addresses this for two different underfill materials, the Namics U8437-3 and the Shin Etsu 5126. While the Namics appears to offer a quite broad ‘window’ this is not necessarily the case for the Shin Etsu.

Effects Of Fillet Thickness On The Delamination Of The Namics U8437-3 And Shin Etsu 5126 Encapsulants In Liquid Shock

Authors: Sandeep Tonapi, Pericles Kondos and K. Srihari

Abstract: This report discusses the effect of flux thickness, belt speed in the reflow oven and reflow temperatures on the collapse of flip chips with Sn/Ag/Cu/In bumps. Comparison is made with the collapse obtained for conventional Sn/Pb bumped chips. It was observed that the amount of flux had a significant impact on the wetting and collapse of this particular lead free alloy. Higher levels of flux resulted in better wetting both on blanket copper substrates as well as actual substrates with Ni/Au pads. This wetting even in the best case was not as good as the wetting of the eutectic Sn/Pb alloy. There was no significant effect of the profile used for the levels of temperature considered.

Flip Chip Assembly With Lead Free Solder - Effects Of Flux Thickness And Reflow Parameters On Wetting And Collapse

Authors: Robert K. Kinyanjui, Balakrishnan Gopalan and K. Srihari

Abstract: Flip chip assemblies with LF-1 no-lead solder joints were investigated in terms of sensitivity to thermal history, using the maximum shear strength at a very low strain rate as an indicator of changes. Prolonged storage at 150oC led to an increasing number of assemblies with down to half the shear strength.

Effect Of Substrate Thickness On Encapsulant Delamination

Authors: Mukul Joshi and K. Srihari

Abstract: Thermal mismatch induced failure of an underfilled flip chip assembly during thermal excursions generally occurs by the fastest of two or more competing damage mechanisms. The present work addresses effects of substrate thickness, die thickness and encapsulant type on one of these. As predicted by FEM delamination of the encapsulant from the surface of the solder joint, and along the die passivation from around the joint toward the die center, was faster on 62 mil thick FR-4 than on 26 mil FR-4. This trend was observed for both 14 and 26 mil thick die of different standoff and layout, and for three different encapsulants.

Effect Of Handling On Subsequent Thermal Cycling Of Encapsulated Flip-Chip Assemblies

Authors: Kevin J. Teed and K. Srihari

Abstract: Model flip chip assemblies underfilled with the Namics U-8347-3 encapsulant were bent once each in a manner that may simulate insertion induced deformation in some applications. After unloading, the assemblies were tested in Liquid-to-Liquid-Thermal-Shock (LLTS). Even minor bending appeared to enhance the subsequent rate of delamination of the encapsulant from the chip passivation around the solder joints. It may also have a minor effect on corner fillet initiation and growth. As usual moisture exposure led to enhanced delamination and corner fillet cracking in subsequent cycling. However, the bending induced damage was not necessarily enhanced by the moisture.

Effect Of Torsion On The Reliability Of Flip Chip Devices

Authors: Balakrishnan Gopalan and K. Srihari

Abstract: This report investigates the effects of twist on first level reliability. The test vehicle was a polyimide passivated die on an FR4 blanket substrate with a Taiyo PSR4000 solder mask. This present preliminary study identified limits of twist beyond which the encapsulant fillets would crack or the encapsulant delaminate. Twist was also found to cause delamination from the substrate in subsequent cycling in some cases.

"Effects Of Pad Metallurgy, Fillet Thickness And Stand-Off On Flip Chip Reliability"

Authors: V. Muthiah and K. Srihari

Abstract: Flip chip reliability is dependent on a large variety of interacting factors. In the present research all combinations of five different pad metallurgies and two different standoff heights were considered for their effects on the thermal shock resistance of 8 mil pitch flip chip assemblies on 62 mil thick FR-4. Failure was found to be dominated by encapsulant fillet cracking followed by corner delamination. The combined effects of fillet thickness, pad metallurgy, and standoff on the progression of such failure in Liquid-to-Liquid-Thermal-Shock was therefore investigated in detail. This report documents the different steps taken in the data analysis in order to separate the experimental noise and bring out the effects of the actual factors under consideration.

Different Thermal Shock Response Of Single And Double Row 5 Mil Pitch Flip Chip Assemblies: Effect Of Gap Size Or Substrate Variations"

Authors: Sandeep Tonapi and K. Srihari

Abstract: Recent research showed unexplained differences between 130mm pitch single perimeter row and 128mm pitch double row flip chip assemblies in Liquid-to-Liquid-Thermal-Shock (LLTS). An increased encapsulant delamination originating from around the larger number of solder joints in the latter assemblies was readily understandable. However, a clearly reduced tendency for the corner fillets to crack and allow for delamination from there was not. It was speculated that the differences might somehow be related to minor differences in standoff, substrate morphologies or (perhaps) local substrate rigidities. A model experiment has therefore been conducted in which these differences were carefully eliminated. The trend was found to still persist.

Effect Of Fillet Thickness And Standoff On Underfill Edge Fillet Cracking

Authors: Muthiah Venkateswaran, Sakethraman Mahalingam and K. Srihari

Abstract: The Dexter EHO544, the Johnson Matthey 8802, and the Kester 9203 flip chip underfill materials were compared in terms of cracking of the edge fillets at the die corners in Liquid-to-Liquid-Thermal-Shock. This phenomenon was found to depend quite strongly on fillet thickness and weakly on standoff across the ranges considered. The Dexter material, in particular, was very susceptible to cracking of fillets thicker than about 10 mil, while the Kester cracked extremely slowly in comparison. It is cautioned that this data is not sufficient to identify the material offering the best reliability of a given flip chip assembly, but the Kester material clearly offers the broadest underfill process window in terms of volume control.

Chemical Degradation Paths To Underfill Adhesion

Authors: Steve Yang, Denis C. Barbini, Vitronics-Soltec and Wayne E. Jones

Abstract: This report investigates the effects of chemical interactions on the behavior electronic packages. Of principal interest are the effects of flux content and residue on encapsulant adhesion. A number of different polymer formulations with unique chemical properties are studied along with predetermined variations in flux chemistry. The effects of flux acid content, residue amount, moisture loading on encapsulant performance are identified.

Underfill Process Codification - A Step-By-Step Guide

Authors: Sandeep Tonapi, Pericles Kondos, Daniel Blass, Peter Borgesen and K. Srihari

Abstract: The capillary flow driven flip chip underfill process may be taken to include selection of equipment (dispenser) and material. Definition of the process certainly involves specification of parameters such as bakeout requirements, substrate temperature, needle size, dispense paths (height above the substrate, distance to chip edge, length of pass), dispense rate, needle temperature, volume in each pass, timing of passes, cure parameters. Optimization of the process and specification of the process windows should minimize important variations and take unavoidable variations (statistics and tolerances) into account.

The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and trouble shooting. The establishment of a substantial database through work done by your materials and equipment suppliers, or by yourself during final qualification or the development of processes for individual applications, is strongly recommended.

The individual sections of this document are carefully organized to minimize the amount of experimental work actually required to reach your goals.

Statistics Of Underfill Edge Fillet Thickness

Authors: Muthiah Venkateswaran, Sakethraman Mahalingam, Sandeep Tonapi and K. Srihari

Abstract: The reproducibility of individual underfill edge fillet thicknesses may seriously affect the statistics of assembly damage and failure. Mechanical loading may tend to favor thick fillets.However, such fillets may crack at the die corners during thermal excursions, allowing for rapid delamination and solder joint failure. On the other had, thinner fillets exert less compression on the interface between the die passivation and the underfill and may allow for such delamination without fillet cracking. The location and width of the acceptable fillet thickness window depends, among other, on the encapsulant and the loading mode of concern.

The present report documents the fillet thickness distributions achieved with three different encapsulants: The Dexter EH0544, the Johnson Matthey 8802, and the Kester 9203. Both widths and means of the distributions varied with the nominal dispense volume, as well as with encapsulant.

"Effects Of Encapsulant, Flux And Solder Mask On Encapsulant Wetting And Void Formation In Flip Chip Assemblies"

Authors: Mukul Joshi and K. Srihari

Abstract: 0.44" area array flip chips were assembled onto FR-4 boards with OSP-coated copper pads using three different no-clean fluxes and underfilled with seven different encapsulants. In spite of a rather large standoff and moderate pitch underfilling tended to lead to a surprising degree of void formation within the solder mask openings. This void formation was found to vary with both encapsulant and flux type, as well as with interactions between these.

Independent model experiments showed the voiding to correlate with the wetting of the encapsulant-flux residue mixture to the solder mask and die passivation surfaces. Voiding was enhanced by improved wetting to the die passivation and/or reduced wetting to the solder mask surface.