Embedded Files
Area Array Assembly Yield Prediction
Authors: G.S.Nathan and K. Srihari
Abstract: This manual presents an overview of the features of the Assembly Yield Prediction program. It describes the installation procedure and the operational details of this software. The inputs of the program include the distributions of bump heights and warpage. The assembly yield is calculated and estimated in terms of parts per million defects. The software is designed for the Windows 9x platform.
Solder Bumping For Ball Grid Arrays
Authors: Jeff Schake, Mohammad Yunus and K. Srihari
Abstract: Solder bumping is an important process step in the manufacturing of BGAs. In mainstream production, a highly robust solder bumping process is essential with requirements of rapid accurate deposition and uniform bump height distribution. Furthermore, this bumping process must be stable and produce high yields in order to support high reliability performance standards. Solder bumping of BGAs using different methods such as solder paste stencil printing and reflow, solder sphere attach with mini-stencil, and solder sphere stencil printing were studied. The bumping was performed for three reasons:
· To investigate alternative ball attach process methods.
· To facilitate building samples for evaluation of Pb-free solders (i.e. aging, shear testing, crack propagation, etc.).
· To allow the completion of Flip-Chip/BGA devices to evaluate the assembly of 1st and 2nd level variables.
Techniques of printing solder paste and mini-stencil sphere placement did not produce desirable results. However, the method of sphere printing has achieved excellent yields with eutectic Sn/Pb and other Pb-free alloy systems. This report outlines the research effort towards the development of a robust solder bumping process.
Chip Scale Package Past Assembly Data
Author: Anthony A. Primavera
Abstract: This report is an overview and summary of the previous assemblies performed during the years 1998 - 1999 Consortium. This information is included since the reliability test results for various CSP devices are now completed. Since vital assembly information is required to assess the reliability results, this data is provided for member companies that do not have access to the previous reports.
Preliminary Evaluation And Assembly With Conductive Adhesives
Authors: Mohammad Yunus, Jaydutt Joshi, Jeff Schake and K. Srihari
Abstract: Electrically conductive adhesive technology is emerging as a potential replacement to lead based soldering. This report presents a brief introduction of the technology and some initial work done with conductive adhesive materials. The focus of this research was the evaluation of an isotropic conductive adhesive as a potential replacement for solder in fine pitch CSP technology, specifically for leadless devices.
A total of 64 leadless devices were assembled with conductive adhesive material and the assemblies were characterized based on their electrical continuity and standoff. Shear testing and pull testing was performed on the assemblies and their strengths compared to conventional Sn/Pb and Sn/Ag solder material.
Characterization Of The Stencil For Test Board #5
Authors: Arun Gowda and K. Srihari
Abstract: The stencil printing process is an integral part of surface mount assembly. The stencil is a key component of the stencil printing process and directly affects the print quality, which in turn affects the assembly yield. Good design and fabrication of the stencil is essential for a sound solder paste printing process.
This report deals with the design and characterization of the stencils designed for Test Board #5. Stencils from two different vendors were characterized. One vendor used laser cutting and the other used electroforming to fabricate the stencils. The design provided to both vendors was the same.
The design and characterization results for the stencils are presented. The two different stencil technologies are compared in terms of the aperture size, pitch, taper, and fiducial location. The accuracy and repeatability of the various aperture shapes are compared and statistical analysis of the data collected is presented.
Assembly Of Micro Smd Packages (Package Af)
Authors: Jaydutt Joshi, Sandeep Tonapi, Mohammad Yunus and K. Srihari
Abstract: Micro SMDs help extend the benefits of flip chip technology (e.g. smaller size, lighter weight, higher I/O density etc.) to the standard surface mount arena. It is designed for the lighter, smaller, and faster devices being used for portable applications. This package can be assembled on to a Printed Circuit Board (PCB) using standard surface mount assembly technology. However, environmental concerns may or may not prompt the use of an underfill or encapsulation process as used in the Direct Chip Attach (DCA) process. Mechanical robustness concerns such as high vibration environments warrant use of an agent to couple the device to the PCB. This report addresses initial experiments that have been performed towards the implementation of the micro SMD package. Total of 480 packages were assembled using four different solder pastes and one no-clean flux. Smaller size of these packages warrants the use of a small nozzle. The combination of low nozzle vaccume, high flux tack, and small part size lead to occurrence (10%) of parts sticking in the flux film. The assembly yield (post reflow) for flux dip process was found to be 99.30%. No defects (post reflow) were observed in the assembly of the packages with solder paste. Some of the assembled packages were underfilled to evaluate the effect of underfilling on reliability. Details and the issues related to the assembly of these packages are studied and documented in this report.
"Assembly Of Csps, Bgas, Wlcsps, And Micro Lead Frame Packages On Test Board " 5"
Authors: Jaydutt Joshi, Mohammad Yunus and K. Srihari
Abstract: Increased product functionality coupled with drastic size reduction places extreme demands on the designer to increase silicon integration and reduce silicon package size. This report discusses the assembly process and issues associated with the assembly of Chip Scale Packages (CSPs), Wafer Level Chip Scale Packages (WLCSPs) and 0.5 mm pitch Micro Lead Frame (MLF) packages. Bridging and voiding was observed in the assembly of leadless packages (Package AQ and Package AN). In particular, bridging was observed in the assembly of package AN on the larger pads ( 30 mil x 14 mil and 30 mil x 12 mil). Additionally, a few high I/O BGAs with 1mm and 1.27 mm pitch were assembled. A total of eleven different types of devices were assembled in this assembly experiment. The motherboard pad metallurgy investigated was Cu OSP. The assemblies were electrically tested and inspected by X-Ray analysis and cross sectioning to check the integrity of the solder joint. The standoff of a few representative packages was measured using a laser profilometer. Leadless assemblies have shown initial assembly problems due to an extremely low stand off height (1-2 mils) and irregular pad/lead configurations (Vision problems). Additionally, experimentation is being performed to determine a viable process window for these CSPs.
Consortium Build At Rockwell Automation
Authors: Anthony Primavera and Mark Dunlap
Abstract: The purpose of this document is to provide information on the PCB board build that was conducted at Rockwell Automation on the 18th and 19th of December 2000. The build was designed to provide a level of comfort that the assembly processes required for BGA’S, CSPs and Leadless components could be implemented in a typical SMT assembly environment. Rockwell provided the assembly environment and staff as part of a joint Consortium build. The design of the PCB included several assembly variables including different pad sizes and routing configurations to determine the effects on assembly and reliability during post build life testing. A lead free 256 I/O FC PBGA component was used to assess the lead free assembly process and subsequently will be used in studying reliability issues. The boards from three different vendors were used to examine variations in materials and processing of vendor to vendor PCB variation. Two different surface finishes namely copper and Ni/Au were used in the assembly. The product was assembled in a (modified) double-sided fashion. In addition to standard CSP assembly the build included lead free assembly of BGA components. Serious issues were encountered during this build related to PCB quality. Several post assembly defects were found to be a result of PCB manufacturing issues.
Characterization Of Test Board #5 (Vendor J)
Authors: Arun Gowda and K. Srihari
Abstract: The Printed Circuit Board (PCB) is a key component in electronic assemblies. It mechanically supports the components and also provides an electrical interconnection between the components. The drive towards fine pitch and ultra fine pitch components has necessitated the use of microvias, double sided boards, and multilayer boards. Test Board #5 is designed to study various issues concerning the assembly of fine pitch Chip Scale Packages (CSPs), Wafer Level CSPs (WLCSPs), and Micro Lead Frame (MLF) packages. In addition, the reliability of blind and buried microvias, effect of voids on the reliability of solder joints, wettability and solderability of various lead-free solders can be studied using this test vehicle.
This report presents the characterization of Chip Scale Package Test Board #5 (CSPTB-5). A dimensional accuracy and repeatability study is presented. Pad size, via size, pitch, and fiducial locations were considered for the evaluation of CSPTB-5. Three CSPTB-5 boards were chosen for this study and the dimensional variations across each board and across different boards were evaluated.
Surface Insulation Resistance And Z-Axis Dielectric Strength Testing
Authors: Jaydutt Joshi and K. Srihari
Abstract: This report presents the results of Surface Insulation Resistance (SIR) and Z- axis dielectric strength testing for high density interconnect substrates evaluated for the Area Array Consortium. Two test vehicles, namely CSP/DCA Test Board–3 (CSP/DCA TB-3) and Test Vehicle–2 (TV-2), were used and evaluated. Four vendors supplied CSP/DCA TB-3, which was manufactured using different technologies and materials. CSP/DCA TB-3 contained two patterns (4 and 8 mil pitch) for SIR evaluation. Patterns were evaluated with and without the application of flux for the degradation in SIR. Serpentine structures and Z-axis comb patterns were designed into CSP/DCA TB-3, to evaluate Z-axis dielectric strength. This test vehicle contained two Z-axis (10 and 20 mil pitch) test patterns. TV-2 was supplied by Vendor E for evaluating the degradation in SIR. It contained 6, 8 and 25 mil pitch SIR patterns. All the samples were exposed to temperature, humidity and bias conditions. For evaluation, the samples were exposed to 85o C, 85% RH and 48 V for 168 hours. It was found that dendrite formation on the patterns (4 mils) causes degradation in the SIR. It was observed that the SIR patterns for the photoimageable dielectric material exhibited the least Sir value as compared to the FR – 4 and Resin Coated Copper (RCC) dielectric materials. TV-3 was used to evaluate the SIR degradation of immersion tin surface finish. All the patterns coated with the immersion tin surface finish showed satisfactory SIR values.
An Overview Of Printed Circuit Board Pad Finishes
Authors: Jaydutt Joshi and K. Srihari
Abstract: The surface finish of the pads on a Printed Circuit Board (PCB) is a critical factor that influences solder joint formation. The quality of the resulting solder joint depends upon the interaction between various factors. These factors include surface finish on the pads, component termination finish, and solder/flux chemistry. The quality of the surface finish directly affects assembly yields and plays a role in solder joint reliability. This report presents an overview of different PCB pad finishes such as Hot Air Solder Leveling (HASL), Organic Solderability Preservative (OSP), nickel/gold, electroless palladium, immersion tin, and immersion silver. The benefits and the drawbacks, as presented in the literature, associated with different pad finishes are discussed in this report.
An Overview Of Test Structures Designed Into Multilayer Microvia Test Vehicle Csptb-5
Authors: Jaydutt Joshi, Anthony Primavera, Madan Mohan Sitaraman and K. Srihari
Abstract: Chip Scale Package Test Board-5 (CSPTB-5) is a high density multilayer test vehicle. It consists of two microvia layers on the top as well as the bottom side. This report provides a detailed description of test vehicle design and construction. The test board contains assembly sites for high density Chip Scale Packages (CSPs), Direct Chip Attach (DCA) components, and microlead frame packages, some of which are routed using microvias in the component pads. This test board also includes microvia chains that will be used to evaluate the reliability of the bare board. Blind and buried via structures are constructed from layer 1 to layer 2, layer 2 to layer 3, and layer 1 to layer 3. This also provides a means to evaluate different via fabrication technologies with respect to via size and via pad size. In addition, CSPTB-5 contains test structures to evaluate the effect of void size on the reliability of the solder joints.
Multilayer Microvia Reliability Evaluation And Failure Analysis
Authors: Jaydutt Joshi and K. Srihari
Abstract: This report summarizes the results of reliability evaluation and failure analysis performed on multilayer microvia interconnect structures. These were designed as a part of the CSP Test Board-5 (CSP TB-5), supplied by Vendor J. The reliability of the multilayer microvia interconnect structures was evaluated using Liquid-to-Liquid Thermal Shock (LLTS) testing. The microvias were fabricated using laser ablation technology and a non-reinforced dielectric. Samples were cross sectioned at time zero to evaluate the vias for parameters such as wall inclination, shape, and plating thickness. Resistance of the via chain was measured at intervals of 125 LLTS cycles. Samples that failed were subjected to non-destructive and destructive analysis in order to fully understand the failure mechanism. It was found that cracks at the via-pad interface were the major cause of failures.
Authors: Arun Gowda and K. Srihari
Abstract: Technological advances and the drive towards fine pitch and ultra fine pitch technology in the electronics manufacturing arena has resulted in the introduction of many new packaging technologies. This report discusses the package construction, the moisture sensitivity, ball shear strength, and thermal aging of some of the new package technologies. The package technologies that are addressed in this report include Ball Grid Arrays (BGAs) with flexible and rigid carriers, Chip Scale Packages (CSPs) with flexible substrates, flip chip CSPs with rigid substrates, and leadless packages. Moisture sensitivity studies were performed at lead-free temperatures (250 °C and 260 °C) to study the effect of the high temperatures on the packages.
The package overview, with the various internal and external dimensions, is presented. For the devices examined, the moisture sensitivity study results show that there is no degradation in the moisture sensitivity of the packages when tested at lead free reflow temperatures. There was no apparent change in physical appearance of the packages after 100 hours of thermal aging. However, there was a significant decrease in the ball shear strength for several of the packages after 100 hours of thermal aging at 150 °C.
A Database Of Area Array Components
Authors: G.S.Nathan and K. Srihari
Abstract: The constructional features of any package widely influence both board design and assembly yields in the electronics assembly. This report discusses a software tool that serves as a knowledge base of constructional details of the area array components that have been characterized in the consortium effort. This software helps the design and process engineers to decide on a specific component construction to package the die. This report also serves as a user's manual for the application – ‘Component Browser’. It describes the installation procedure and the operational details of this software.
Characterization Of Package Ag, Ah And Ai
Authors: Madan Mohan Sitaraman and K. Srihari
Abstract: Package AG, Package AH and Package AI are all CSPs which have a die mounted on a flex substrate with an overmolded wirebond construction. Of the packages (samples) considered in this study, only Package AH had wire-bonded first level test die interconnections while Package AG and AI were daisy chained on the substrate of the component. An effort was made to characterize these packages with respect to their physical dimensions and also with respect to their behavior in moisture test conditions. Components were subjected to JEDEC Level-3 testing to evaluate the occurrence of moisture-induced defects in these packages. An optical interferometer was used on these packages to measure critical parameters such as the bump height, solder ball diameter, and coplanarity. Finally, cross-sectional analysis was performed to determine the bump metallurgy and the constructional details of the package.
Preliminary Characterization Of Package Ak, Am, An, & Ap
Authors: Madan Mohan Sitaraman and K. Srihari
Abstract: Chip Scale Packages (CSP)'s used in the Area Array Consortium, AK, AM, AN, and AP were characterized with respect to their physical dimensions. Additionally, they were characterized with respect to their behavior under various test conditions such as moisture loading. Cross-sectional analysis was performed to determine the bump metallurgy and the constructional details of the package. The physical dimensions of the package were recorded using a Co-ordinate Measurement Machine (CMM) and a graduated cross-section microscope. The aforementioned components were subjected to moisture sensitivity testing to evaluate the rate of moisture absorption and desorption in these packages. Absorption studies were done on Package AP, AM and AN by subjecting them to 30oC, 60% RH conditions. Although, package AP has the highest level of moisture absorbtion, it has a low absorbtion rate. It also takes a relatively long duration to achieve saturation, possibly due to the large area of the substrate exposed on the bottom of the package. Package AM and AN do not absorb as much moisture as compared to Package AP. These two packages (AM and AN) saturate much earlier, around 100 hours.
Assembly Process Characterization For Pb-Free Through-Hole Soldering
Authors: Hendra Hartono, Mohammad Yunus, Mike Meilunas and K. Srihari
Abstract: As part of the lead free assembly experimentation performed by the Universal Instruments Research Consortia, the robustness of through hole solder joints was investigated. Comparison of wave soldering and Alternative Assembly and Reflow Technology (AART) or Pin-In-Paste (PIP) was performed to examine the process steps and resulting joint quality of lead free solder alloys. Several Pb-free solder alloys including Sn/Ag/Cu, Sn/Ag, and Sn/Cu were studied to compare the two methods in terms of the solder joint formation. In order to qualify the solder joint formed by each of these two methods, both destructive and non-destructive testing was performed. The results were then compared with a new solder joint standard guideline that was developed at Universal to judge the robustness of the solder joint that was formed. In addition, board warpage was measured to investigate the effects of the two soldering methods, on the quality of the board. This report details the investigation that was undertaken in comparing these soldering methods. It also discusses the effect of each soldering method in detail. The results indicate that while the lead free solder wave assembly process gave superior joint formation, the Alternative Assembly Reflow Technology method gave sufficient joint fillets in most cases.
Author: Paresh S. Limaye
Abstract: Increased consumer demand for cheaper and more powerful electronic devices has resulted in increased packaging density and higher functionality electronic packages. At the same time, heightened environmental consciousness among consumers is pushing the industry towards eliminating lead from the devices. Therefore, suitable lead free solder alloys must be identified that can meet functionality, cost and reliability requirements. Unfortunately, not much is known about the behavior of lead free solders under different fatigue and thermal conditions and no standardized package exists which can be used for evaluating the different alloys.
Thus, a methodology for designing generic test packages was developed for evaluating the mechanical properties, assembly and reliability issues associated with lead free alloys. The basic concept of the generic Flip Chip Plastic Ball Grid Array (FC-PBGA) package lies in creating a global Coefficient of Thermal Expansion (CTE) mismatch between the component and the board. Package warpage and stiffness are controlled by altering die materials (glass, silicon, steel etc) and package structures (balanced, i.e. symmetric about mid-plane and unbalanced, i.e. non-symmetric about the mid-plane).
Classical Laminate Plate Theory (CLPT) and Finite Element Analysis (FEA) were utilized for evaluating primary design configurations. Once the basic designs were finalized, a manufacturing process was developed with readily available equipment and materials. Solder bumping, encapsulant dispense and die placement processes were developed.
Package CTE was evaluated using Moiré Interferometry. Package warpage was evaluated with Shadow Moiré techniques and with 3-D laser scanning. Package stiffness properties were evaluated by performing 3-point bend tests. Moisture sensitivity tests were also performed to evaluate if the mechanical integrity of the package is maintained if exposed to moisture.
The FC-PBGA package developed satisfies most of the design requirements. Results between predicted and measured package properties correlate well. CLPT proved to be an excellent tool (compared to FEA) for rough estimation of package properties and to study parameter variation effects. The concepts developed and implemented in this package can be scaled down to chip scale sizes as well. Universal Instruments is currently implementing the FC-PBGA package in a large number of studies within the Area Array Consortium.
Assembly Process For Lead-Free Bgas
Authors: Mohammad Yunus and K. Srihari
Abstract: In the recent past, there has been an increasing concern within the electronics manufacturing industry about the environmental impact of lead-based solders. Alternative solder materials are being developed. The choice of a specific solder alloy may very well depend on the technology and the component mix on the Printed Circuit Board (PCB). Each component technology, namely through hole, surface mount and area array, will have to be studied separately and also in conjunction for their compatibility with lead-free solders. BGA components with lead-free solder bumps were assembled on various pad metallurgies as a part of the overall lead-free program at Universal Instruments Corporations Area Array Consortium. BGA components with 256 Input/Output (I/Os) and a pitch of 1.27 mm with different solder alloys [Sn(96.5)/Ag(3.5), Sn(95.5)/Ag(4.5)/Cu(0.5), Sn(96.2)/Ag(2.5)/Cu(0.8)/Sb(0.5) and Sn(63)/Pb(37)] were assembled on standard pad metallurgies such as Cu OSP, Ni/Au and Ni/Pd. The use of these pad metallurgies helped to study the relevant assembly issues with lead-free solders and to evaluate their reliability. These assemblies were electrically tested and inspected by X-ray analysis and cross sectioning to check the integrity of the solder joint. The stand-off and the warpage of a few selective samples were measured using a laser profilometer.
Lead-Free Assembly Of Leadless Csps
Authors: Mohammad Yunus, Jaydutt Joshi and K. Srihari
Abstract: This study involved the assembly of Ball Grid Array (BGA) and leadless Chip Scale Packages (CSP)s with lead-free solder material. The BGA component assembled was a 256 I/O, 1.27 mm pitch generic flip chip BGA developed for lead free experimentation within the Consortium. Four types of leadless CSPs with pitch of 0.5 mm were assembled in this study. The solder alloy used for assembly was eutectic Sn/Ag (96.5/3.5) and the motherboard pad metallurgy evaluated was Cu OSP. The assemblies were electrically tested and inspected by X-ray analysis and cross sectioning to check the integrity of the solder joint. The standoff and warpage of representative samples was measured using a laser profilometer. Assembly results indicate a strong yield - pad size interaction. Devices assembled with attachment pads on the circuit board larger than the device lead width were prone to bridge defects. The leadless devices when assembled have an extremely thin solder joint (1-2 mils) 25-50 microns. The space between the device and the top of the circuit board does not allow for deposition of solder without the probability of bridging for apertures and pads larger than the lead width. The paste is compressed during soldering and forms a bridge during reflow.
Lead-Free Bga Assembly Process
Authors: Mohammad Yunus and K. Srihari
Abstract: Tin/Lead (Sn/Pb) solders have been extensively used in the electronics industry as an interconnecting material. Environmental concerns of lead-based soldering have prompted an increase in the research activities trying to identify a "drop in" replacement for lead-bearing solder alloys. Several concerns, including material and process issues, need to be addressed before a suitable alloy is chosen. Among the processes, reflow soldering is extremely critical as the solder joint is formed during this phase of assembly. Many lead-free solders have a higher melting point than eutectic Sn/Pb. This necessitates the examination of metallurgical and physical changes that components and PCBs may undergo during a higher peak temperature reflow. In addition, the multiphase alloys being considered do not have single melting solidification point, thus affecting the phase formation during the cool down from liquidous. The issues and concerns that relate to the reflow process have to be completely understood. This report discusses the reflow profiles generated for four different lead-free solders. An attempt has been made to study some of the issues pertaining to lead-free soldering in this initial study directed at deriving a better understanding of the necessary requirements for lead-free soldering.
Reflow Profile Development For Lead - Free Solders
Authors: Paresh Limaye and James Pitarresi
Abstract: This report describes an assembly process developed for lead free Generic FCPBGA devices [Limaye 1999] designed and fabricated in Universal Instrument Corporation 's SMT Laboratory. Components (256 I/O and 1.27 mm pitch) were bumped with different lead free alloys Sn(96.5)/Ag(3.5), (Sn(96.2)/Ag(2.5)/Cu(0.8)/Sb(0.5)) and Sn(94.5)/Ag(4.0)/Cu(0.5) as well as eutectic Sn(63)/Pb(37) spheres. The components were assembled on corresponding BGA pad sites on two test vehicles using standard surface mount technology. Reflow profiles developed for lead free alloys in previous research [Yunus, 1999] were utilized. A total of 354 assemblies were made. Only four 'time zero' failures were observed and all of them were attributed to missing solder bump on the component due to the bumping method. These assemblies are used in four experimental projects. A brief description of the experiments is included in the body of the report.
Influence Of Reflow Atmosphere On Lead-Free Processing
Authors: Mohammad Yunus, Vinod Mohan and K. Srihari
Abstract: The implementation of lead-free solders requires a robust assembly process. The reflow stage of the surface mount assembly process is perhaps the most critical process step, as the final solder joint is formed during this stage. Many lead-free solders have a higher melting point than eutectic Sn/Pb. This necessitates the examination of metallurgical and physical changes that the materials set undergoes during processing and their effect on the assembly process. Lead-free solder alloys have shown poor wetting ability with standard Cu OSP metallization and this is primarily attributed to the incompatibility in the material system being used. The reflow atmosphere is a critical assembly parameter as it has been shown to affect assembly yields and reliability with Sn/Pb solder material. However, air has been successfully used as a reflow atmosphere and this has helped in cost effective electronics manufacturing. With the push towards lead-free soldering, the effect of reflow atmosphere on assembly needs to be investigated.
Alternate Surface Finishes For Lead-Free Soldering
Authors: Mohammad Yunus, Vinod Mohan and K. Srihari
Abstract: The complete removal of lead from electronic products requires its elimination from solder materials, component terminations and board finishes. The most commonly used board finish in today’s electronics industry is Sn/Pb HASL. Along with the effort to study Pb free solder materials, an effort has been undertaken to study alternate Pb free surface finishes. This study investigates alternate surface finishes of Cu OSP, Ni/Au, Ni/Pd, Immersion Sn and lead-free HASLs. Materials related properties such as wetting capability and shear strength of different lead-free solder alloys on these finishes were investigated. Additionally, BGA devices were assembled and assembly issues arising from these different finishes were addressed. The studies show very similar performance of the different surface finishes from a wetting and shear strength perspective with the exception of Ni/Au and Cu OSP. The Ni/Au surface finish shows significantly superior wetting, while Cu OSP shows slightly degraded wetting with the different lead-free solder alloys. From an assembly perspective, no anomalies were observed between the different surface finishes.
Effect Of Pb Contamination On Lead-Free Solders
Authors: Mohammad Yunus, Denis Barbini and K. Srihari
Abstract: Lead-free solders are being actively investigated as alternative solder materials due to the environmental effects and the health hazards of existing lead based solders. It is more than likely that the switch to lead-free soldering will occur in phases, whereby some amount of lead-based solder material will co-exist with lead-free materials in the electronic system. This research effort studied the metallurgical compositions in the final solder joint with the contamination/presence of Pb in lead-free solder joint. The alloy systems investigated were Sn/Ag (96.5/3.5), Sn/Ag/Cu/Sb (96.2/2.5/0.8/0.5) and Sn/Bi (42/58). Different percentages of Pb contamination were introduced in the lead-free solder material and analysis was performed by utilizing a Differential Scanning Calorimeter (DSC). Changes in the melting points as well as formation of low melting phases were observed. Any unique metallurgical reactions were also captured by cross sectional analysis.
Testing And Evaluation Of Lead-Free Solder Pastes For Surface Mount Technology
Authors: Vinod Mohan and K. Srihari
Abstract: This study evaluates different lead-free solder paste compositions from different vendors and compares them with eutectic tin-lead solder, based on analytical and process tests. The lead-free compositions evaluated were Sn/Ag (two vendors) Sn/Ag/Cu (two vendors), Sn/Cu and Sn/Ag/Cu/Sb (one vendor each). The analytical tests performed were viscosity measurement, solder ball test, slump test, spread test and tack test. The process test conducted was a printability test. The data from the tests was compiled and used to rank the solder pastes being evaluated. The procedure and results of each test is included in this report. Among the lead-free solder pastes evaluated, the Sn/Ag/Cu alloy composition emerged as the best performer based on the tests conducted. There was not any marked difference in performance of the similar compositions for different vendors.
Self-Centering And Pull Back Property Of Lead-Free Solder Alloys
Author: Mohammad Yunus
Abstract: Area array devices have been shown to self-center during the reflow process. This phenomenon has helped to achieve improved yields when compared to the assembly of conventional peripheral leaded packages. Self-centering has been attributed to the minimization of the free surface energy and surface tension of molten solder. Work however, has been predominantly performed with an alloy of tin and lead Sn/Pb. With the increasing use of lead-free solder materials, the self-centering property of the new solders is critical, as it has a direct effect on assembly yields, solder joint formation, and the ability of the material to coalese into a single spherical ball. As a part of the overall lead-free program within Universal Instruments Corporation’s Area Array Consortium, studies were performed to evaluate the pull back and self-centering property of three lead-free solder alloys. Two different experiments were performed to study the solder pull back and self centering property of lead-free solder alloys. The ability to pull back was evaluated by printing solder paste at an offset (50 and 75 %) followed by reflow without any component placement. Additionally, the ability to self center was evaluated by placing area array components at pre-determined offsets (50 and 75%) followed by reflow. The lead-free alloys exhibited sufficient pull back and self centering even in cases where the offset was 75 % of the pad diameter.
Shear Strength Of Lead-Free Solder Alloys
Authors: Mohammad Yunus and K. Srihari
Abstract: Eutectic Sn/Pb solder has been widely used as a soldering material in the electronics industry, but it has been documented that there are environmental and toxicity issues associated with lead based alloys. The electronics industry has been forced to look for an alternate soldering alloy. An initial study was conducted to study the mechanical strength of lead-free solder joints. The work reported here examines the shear strength of two lead-free alloys on standard pad metallurgies such as Cu OSP, Ni/Au, Ni/Pd and compares their performance against the standard eutectic Sn/Pb alloy.
The effect of isothermal aging of the solder joint on shear strength was also evaluated. The effect of pad geometry such as pad defined and solder mask defined, was also evaluated. The intermetallic growth for the lead-free alloys under evaluation was characterized to correlate with the mechanical strength. Shear strength was evaluated by shear testing using an Instron Materials Tester and the maximum load and displacement at maximum load data was analyzed to provide insight into the mechanical strength of solder joints. The results indicated that the failure mechanism was ductile and there were no indication of brittle failure even after isothermal aging at 125°C. After 500 hours of aging, there appeared to be a transition to brittle failure mode, but there were no indication of a complete brittle failure even after aging for 1000 hours. The shear strength of lead-free alloys were comparable to eutectic Sn/Pb alloy.
Solderability Evaluation Of Components Bumped With Lead-Free Alloys
Authors: Mohammad Yunus and K. Srihari
Abstract: Environmental concerns of lead-based soldering have prompted the move towards identifying a suitable lead-free alternative. A lead-free system would not only consist of soldering material that is lead-free, but also component terminations and Printed Circuit Board (PCB) surface finishes that are also lead-free. This warrants the use of lead-free solder bumps on area array components. Research has been focused on defining the relative solderability performance of lead-free bumped components with that of eutectic Tin/Lead (Sn/Pb) alloy. The lead-free alloys investigated did not reveal any solderability issues for the various test conditions. However, the components bumped with the Sn/Pb alloy indicated some solderability issues after 48 hours of baking at 150°C. This report discusses the testing methodology adopted and the results observed.
Wetting Ability Of Lead-Free Solder Alloys
Authors: Mohammad Yunus and K. Srihari
Abstract: The electronics industry is being pushed towards eliminating lead from its products. This has stimulated an increased interest in alternatives to traditional eutectic Sn/Pb solders. In an attempt to set a baseline for further studies in lead-free alloys, an initial study was conducted to study the wetting abilities of a few lead-free solder alloys. The work reported here examines the wetting ability of a few promising lead-free solder alternatives on Cu OSP, Ni/Au and Ni/Pd pad metallurgies. The effect of multiple reflow on the wetting ability and the effect of flux on the wetting ability were also investigated. Although this is not a comprehensive evaluation of all the factors, the results give us some valuable insight into the wetting ability of lead-free alloys. Solder wettability was determined by performing an area of spread test, by measuring the diameter of spread and characterizing the wetting ability based on the wetting angles. The results indicated poor wetting performance of lead-free alloys on CuOSP pad metallurgy; however their performance was comparable to eutectic Sn/pb solder on Ni/Au and Ni/Pd pad metallurgy. No significant effect of multiple reflow cycles was observed on the ability of lead-free solders. It is important to note that this preliminary study is to be repeated as materials are developed for lead-free. The fluxes used in today’s commercially available solder paste are based on Sn/Pb alloys and will most likely need to be reformulated for the more stringent requirements of lead-free systems.
Packaged Devices And Lead Free Activities: Summary
Author: Anthony A. Primavera
Abstract: This report is a final overview and summary of the area array consortium activities related to assembly and test of packaged devices and additionally discusses lead free soldering activities. This overview is a summary of the consortium development for the year 2000. A separate summary is presented in [Borgesen, 2001] for the year 2000 direct chip attach program. A total of almost 50 reports have been prepared for the year 2000 area array efforts which discuss the following topics:
· Circuit Boards
· CSP/BGA Components
· Assembly
· Rework
· Assembly Materials (Paste, stencils etc.)
· Reliability Testing
· Nickel Gold Metallurgy
· Lead Free Materials
· Lead Free Assembly
· Lead Free Reliability
Some of the projects completed this year were continuations of previous studies, such as thermal cycle testing, while other studies were started and completed within the 2000 work scope. Further information about each topic is available in supporting documents and reports, which are referenced in this report. Additional information is available in the year 1999 and 1998 Area Array Consortium CD-rom. While activities included both tin / lead (Sn/Pb) as well as lead free solder alloys, this overview will combine aspects of both technologies where important and relevant. For example, a discussion on rework or assembly will contain issues related to BGA and CSP devices for both lead bearing and lead free solders. Issues related strictly to lead free such as wave soldering with lead free alloys, will be discussed as well.
Reliability Modeling Of Chip Scale Packages
Authors: James M. Pitarresi, Ram Mohan Sitaraman, Sundar Sethuraman and Bala Nandagopal
Abstract: A finite element based approach for estimating the thermal cycling reliability for chip scale packages is presented. The methodology is based on Anand’s viscoplastic constitutive law for the solder response and Darveaux’s crack growth-rate model for solder fatigue. A Weibull two-parameter failure distribution is assumed. Three-dimensional finite element models were built for each of the over thirty packages studied. The number of cycles to fifty percent package reliability was estimated for two different thermal profiles (0oC to 100oC, 20 minute; -40oC to 125oC, 60 minute). Good correlation between the measured and predicted life was observed for many of the packages that have completed their testing. The correlation was typically within the expected
1.5X error band of the method. Notably, poor correlation was observed with some package families such as the wafer-level CSPs and flex-based BGAs. This is could be attributed to differences between the components modeled (as developed from vendor-supplied drawings) and actual “as tested” component construction. In addition, the wafer-level CSPs present new modeling challenges due to their small size and inclusion of thin but significant material layers. Further work needs to be done to improve the modeling results for these packages. A small number of parameter studies were performed using the three-dimensional models. It was observed that increasing the flexibility of the elastomer layer in flex-based devices resulted in a higher joint life while a larger via size and decreased die thickness both produced a modest joint life increase.
Reliability Assessment Of Leadless Chip Scale Packages In Air To Air Thermal Cycling
Author: Michael Meilunas
Abstract: The introduction of leadless chip scale packages has been driven by two major factors: the desire for smaller, more space efficient designs and the required elimination of lead (Pb) from electronic products. By removing the solder ball or component lead at second level interconnection, package suppliers are offering components with minimal thickness. This approach however, leaves the choice of attachment material to the assembler. This study involved evaluating the second level reliability of four 0.5 mm pitch leadless package assemblies which had been assembled to 62 mil thick copper OSP boards using Sn/Pb and lead free solder materials. Each package type was assembled to four motherboard land patterns in order to evaluate the effects of interconnection shape and size on yield and reliability. A 0 to 100°C, 20 minute air to air thermal cycle was used to accelerate solder fatigue. In-situ monitoring was used to determine when failures occurred, while cross-sectioning and dye penetration analysis were performed to determine failure mechanisms. For this experiment, three materials were used in assembly, namely 96.5/3.5% Sn/Ag, a silver filled conductive adhesive, and a eutectic Sn/Pb baseline solder.
Microvia Reliability Evaluation And Failure Analysis Of Csptb-5 (Vendor Aa)
Authors: Arun Gowda and K. Srihari
Abstract: The increase in packaging density and the advent of fine pitch and ultra fine pitch area array components necessitates the use of multilayered boards and microvia structures to interconnect the components. The use of microvias as an interconnect structure is common today and reliability greater than the components is required. This study involves the reliability evaluation of the microvia structures on the microvia test site of CSPTB-5 supplied by Vendor AA. The evaluation takes into consideration both blind and buried microvias and also various via and pad sizes.
This study is in continuation with the microvia reliability evaluation program at Universal Instruments Corporation. This report presents the results of the initial visual and electrical inspections, LLTS (Liquid to Liquid Thermal Shock) cycling data, and failure analysis. Many time-zero failures were observed. The layer 1-2 vias performed the best in the LLTS cycling and showed no failures due to “thermal shocking”. Various failure mechanisms were observed and are presented in this report. Also preliminary results of microvia evaluation of different test boards from the same vendor and a different vendor are presented.
Study Of Solder Joint Embrittlement For Nickel Gold Pad Finish (I)
Authors: Paresh S.Limaye and James M.Pitarresi
Abstract: Solder joints assembled on Nickel-Gold pad finishes have been known to exhibit a brittle behavior in shear testing after aging. To date speculative reasons for the problem have been suggested in literature, however no conclusive reason has been assigned as to the root cause of this embrittlement phenomenon. Most literature points to a ternary Ni/Sn/Au intermetallic [Cotts et al, 1999] [Mei, Z. et al, 1998].
In this experiment, nickel-gold plated boards from twenty-eight vendors were investigated with regard to the solder joint embrittlement phenomenon. The goal was to determine the board parameter(s) needed to predict the defect in a given board as well as survey the PCB industry for the occurrence of the phenomena. Initially, solder joint shear testing was conducted to see if any trends could be observed with respect to the mechanical properties of the joint, however no such trends were observed. It was also observed that the thickness of the nickel and gold platings in this experiment was not related to the occurrence of brittle failure.
SEM analysis revealed that all of the brittle samples analyzed contained very rough and uneven intermetallic layers and nickel, tin and gold were observed on the fracture surfaces. However, SEM analysis of the ductile samples revealed smooth and uniform intermetallic layers with only nickel and tin present. This indicates that the amount of gold-tin intermetallic located at the pad/ball interface in the ductile joint is relatively insignificant when compared to a brittle joint. Additionally, all the brittle failures observed before aging were attributed to improper fluxing and poor solderability to the printed circuit board pads. The SEM analysis has been carried out on a limited number of samples and further analysis is required. A second round of testing is proposed in which all the boards tested will have solder mask defined pads. This will reduce the amount of erroneous data present due to pad rip-offs from the board as the solder mask holds the pad in place and only the solder joint is sheared.
Nickel Gold Pad Finish Brittle Interfacial Fracture/Embrittlement Investigation : Part Ii
Author: Paresh Limaye
Abstract: Electroless Nickel/Immersion Gold (ENIG) is a commonly used pad finish in the electronics industry. This finish provides a flat solderable surface for further soldering and assembly operations. However, an early failure has been observed in the solder joints assembled on this finish in which the bulk solder delaminates from the intermetallic layer. To date, no conclusive cause for the occurrence of this phenomenon has been established. This research is an extension of a previous research project [Limaye, 2000].
CSP TB4 (Test Board 4) was supplied to 6 vendors for plating with ENIG finish. These boards were then bumped with Sn/Pb as well as Sn/Ag (96.5/3.5), Sn/Ag/Cu (95.5/3.8/0.7) and Sn/Ag/Cu/Sb (96.2/2.5/0.8/0.5) alloys. Samples were subjected to isothermal aging, LLTs and AATC. A shear test was performed on these to evaluate the solder joint strength, integrity and fracture surface.
No brittle interfacial fractures have been reported on any of the test combinations thus far. In general, the lead-free alloys show comparable or greater shear strength than the Sn/Pb alloy.
A case study was also carried out in which boards known to exhibit the brittle interfacial fracture were bumped with lead-free alloys. It was seen that Sn/Pb and Sn/Ag exhibited a partial delamination. However, Sn/Ag/Cu and Sn/Ag/Cu/Sb showed a clear ductile failure. However, the sample size for this case study is small. More intensive efforts need to be carried out to validate these findings.
Authors: G.S.Nathan and K. Srihari
Abstract: The data generated in the area array consortium for second level reliability experiments on electronic packages is extremely voluminous. Hence, analysis of the data consumes large amounts of time. In order to be able to find trends in the data with respect to certain key parameters efficiently, one needs to introduce a certain level of automation. This was accomplished by implementing a software based 'smart system' called the reliability module. The module proposes a method to catalog the data and retrieve it faster using the relational database approach. The module allows the user to find exact as well as 'close' matches to the requested test parameters in the search capability. This user - friendly module has been programmed using Microsoft Visual Basic 6.0 and uses Access 97 as the database. This report describes the operational details of the software and hence serves as a user's manual for the application – ‘Reliability Module'.
Mechanical Reliability Of Lead-Free Bgas
Authors: Mohammad Yunus and K. Srihari
Abstract: A solder joint in an electronic assembly fulfills both electrical and mechanical functions. In this study, the mechanical reliability of lead-free BGA solder joints was investigated and the performance of alternate lead-free solder materials were compared. Mechanical testing of lead-free BGAs was performed by cyclic torsion testing. The characteristic life of the different solder materials was evaluated and compared. The lead-free alloys that were investigated showed higher characteristic life as compared to standard Sn/Pb solder material. Sn/Ag/Cu and CASTIN solder alloys showed failure mechanisms similar to the eutectic Sn/Pb alloy. The Sn/Ag alloy showed brittle failure at the interface between the solder and Ni/Au attachment pads.
Resistance Monitoring Of Lead-Free Solder Alloys
Authors: Michael Meilunas and Anthony Primavera
Abstract: During Universal Instrument’s attempt to characterize the reliability of several lead-free solders an unexpected phenomenon was observed. It was found that, during air to air thermal cycling with continuous monitoring, certain BGA packages utilizing Sn/Ag and Sn/Ag/Cu lead free solder had multiple short duration resistance spikes mid way through thermal cycle testing. While this phenomenon resulted in the failure of the packages by definition of [IPC-SM-785], joint inspection of sample packages by continuity testing failed to locate an open solder joint. The packages were returned to test and continued to demonstrate this phenomena. After approximately several hundred additional thermal cycles, the resistance peaks ceased and a low resistance level was observed. Testing continued until eventual full failure of the solder was observed and permanent opens were found with continuity testing. This paper describes the phenomena as observed by the experimenters and documents the actions taken to verify the results. A brief discussion is included which highlights several theories as to the cause of the phenomena and what steps are being taken in further investigations.
Update To Reliability Testing Results Of Chip Scale Packages
Author: Michael Meilunas
Abstract: Evaluation of a CSP assembly’s performance involves the investigation of many factors including printed circuit board parameters, assembly techniques, package construction details and package materials. The typical in-field failure mechanism of a CSP is second level solder joint fatigue due to differences in thermal expansion between the component and printed circuit board. Thus, Universal Instruments utilizes accelerated air to air thermal cycling (ATC) to evaluate package reliability since ATC typically results in solder fatigue failures. This report will discuss current and recently concluded tests and is meant to append ‘Reliability Testing Results for Chip Scale Packages – Phase II’ of December 1999.
Effect Of Voids On The Reliability Of Solder Joints
Authors: Mohammad Yunus and K. Srihari
Abstract: Voids in solder joints have been considered as a defect in electronics assembly. The factors that affect void formation are complex and involve the interaction of many other factors. There are no established standards for void size and void area in a solder joint for it to be deemed defective. Inspection criteria have been very subjective. The effect of voids on the reliability of solder joint may depend not only on the size, but also on frequency and location. This study is focussed on investigating the effect of voids on the reliability of solder joints. The size, location and frequency effects on the reliability were studied. Testing was done by mechanical deflection testing (Torsion) system and Air to Air Thermal Cycling ( -40°C/125°C). Failures were analyzed for the failure modes by cross sectional analysis. The results indicate that voids reduce the life of the solder joint. Voids which are greater than 50 % of the solder joint area, decrease the mechanical robustness of the solder joints. Small voids also have an effect on the reliability, but it is dependent on the void frequency and location. Additionally, voids often coincide with microvia in pad assemblies, in which there is an entrapment of air in the via during the assembly process. These voids are typically the diameter of the microvia and have shown to have reduced the mechanical robustness of the joint in many cases. This report covers the effect of voids on the reliability (mechanical robustness and thermal-mechanical) of solder joint. Additionally, a thermal-mechanical (by FEM) evaluation of the effect of voids in area array solder joints has been performed by[Pittaressi, et al., 1999] finite element modeling.
Improving Copper Coupon Wetting For Use On Rework Machines
Author: Martin K. Anselm
Abstract: Rework is a process that is used in many assembly operations. Like every process in integrated circuit board manufacturing, as packages get smaller the assemblies have to adapt. Rework is not immune to this problem. Packages are becoming much more difficult to remove and replace, while damage to the pads and surrounding components is more prevalent. One of the many challenges in the rework process is the removal of excess solder from the pads of a printed circuit board (PCB), otherwise known as redressing or scavenging. Current scavenging methods include; solder wicking with a braid, a convective process called hot air scavenging, vacuum de-soldering pump, and finally a wettable or porous coupon to remove the excess solder. Wicking becomes very difficult for small pad sizes and very often damages solder masks, while the scavenging and de-soldering process are slow and do not have uniform results [Mohan et. al., 2000-C]. Of the current redressing techniques, copper coupon solder removal has shown promising results for fine pitch applications. It has been shown that surface roughness and finish effects wetting of molten solder to that surface. It is postulated that if coupons could be given a certain roughness they may be able to remove more solder due to improved wetting an increased surface area. Sandpaper of 600, 400, 320 and 240 grit were used on two types of solder platforms to determine which roughness caused the greatest improvement in wetting. The sample surface with the most improvement in solder wetting was then used for scavenging actual sites on a PCB. Based on the uniformity of the residual bumps, and their height, it was possible to determine if the roughened copper coupons were an improvement over smooth as received coupons. It was found through this research that linearly sanded copper coupons, using 240 grit sandpaper was the most successful in removing residual solder from fine pitch PCB solder pads.
Rework Of Lead-Free Assemblies
Authors: Madan Mohan Sitaraman and K. Srihari
Abstract: This study developed a preliminary process for the rework of lead-free BGAs. The various issues and concerns that are pertinent to the individual steps of rework were investigated and recommendations were provided for a suitable process. With higher peak temperatures being the main challenge, the consequence of using correspondingly higher temperatures for the heater settings were studied and solutions provided to avoid some of these problems. A 256 I/O Flip Chip Plastic Ball Grid Array (FCPBGA) package constructed for this project with three different lead-free solder bumps was used for this study. These components were assembled on CSP Test Board-1 and BGA Consortium Test Vehicle-3, with different pad metallurgies. Components were reworked and then subjected to reliability testing to compare their lifetime with conventional eutectic tin-lead alloys on the same component. Reliability testing was completed up to 8500 cycles to date (currently in progress). Failure analysis showed one failure observed at 3000 cycles due to an open corner joint. In addition, several samples failed at 6,000 to 8,000 cycles.
Process Development For Rework Of 0.5-Mm Pitch Chip Scale Packages
Authors: Madan Mohan Sitaraman and K. Srihari
Abstract: With the advent of Chip Scale Packages (CSPs), the electronics manufacturing industry is faced with several challenges in the rework environment. Some of the challenges include the small size of the component and the solder ball, fine pitch of the components, small pad size, and a high number of I/Os. Another challenge is the board thickness, which is often 20 mils or below. This report discusses the rework of a 0.5 mm CSP. A generic process for the rework of fine pitch (less than 0.75 mm pitch) packages was developed. A set of assemblies has been reworked and is presently undergoing reliability evaluation. Various issues such as profiling, component removal, site redressing, fluxing, and replacement are discussed in detail. Multiple inspection methodologies are described and recommendations for successful rework are provided.
Rework Of Fine Pitch Chip Scale Packages
Authors: Madan Mohan Sitaraman and K. Srihari
Abstract: With the advent of Chip Scale Packages (CSPs), the electronics manufacturing industry is faced with several challenges in the rework environment. Smaller package and solder ball sizes, decreasing pitches and space limitations complicate the rework procedure. This report discusses the rework of fine pitch CSPs (less than 0.75 mm pitch). A generic process for the rework of fine pitch packages was developed. A set of assemblies of CSPs with I/Os ranging from 8 to 328, on a pitch of 0.5 mm, was reworked and is presently undergoing reliability evaluation.
To address issues specific to fine pitch, experiments were also conducted on CSPs with reference to site cleaning, fluxing and placement to evaluate the different techniques and methodologies. In addition to the conventional CSPs, certain “bump-less” CSPs were also reworked using the techniques selected from previous experiments. These bump-less packages needed solder deposition before assembly and a localized printing process was developed to address this issue. Additional work is planned for designing and evaluating rework processes for the bump-less packages.
Various issues such as profiling, component removal, site redressing, fluxing, and replacement are discussed in detail. Multiple inspection methodologies are described and recommendations for successful rework are provided.
Rework Of Chip Scale Packages On Via-In-Pad Assemblies
Authors: Madan Mohan Sitaraman and K. Srihari
Abstract: Via-in-pad structures are being increasingly used to cope with higher density and reduced pitch in circuit boards. In these pad structures, vias are drilled on the pad to route it to the next layer. The rework of chip scale packages that are assembled on sites with via-in-pad structures offers several challenges in addition to the fine pitch of the chip scale packages used. One of the challenges is the removal of voids formed during assembly. In this research effort, chip scale packages were assembled using a rework station and then reworked using the conventional rework process. Efforts were made, particularly in the component removal and site redressing process, to eliminate voids that resulted from the use of via-in-pad structures. Also, a new process sequence was used to apply flux to the bumps of the package. It was observed that most of the voids were removed during the component removal process when the solder joint was subjected to a second reflow (after assembly).
Alternative Flux Application Techniques For Flip Chip Assembly: Stencil Printing
Authors: Sandeep Tonapi, Sakethraman Mahalingam, Kaustubh Nagarkar and K. Srihari
Abstract: Alternative methods of applying the flux needed for flip chip assembly are currently under investigation. A process involving stencil printing of a tacky flux was developed and evaluated. Process development work involved stencil design, screening of available fluxes and optimizing the stencil printing parameters. The resulting resistance to moisture exposure, popcorning and thermal shock was found to be similar to that achievable using flux dipping. In both cases the Namics U8437-3 encapsulant performed better than the Dexter FP4549.
Optimizing Substrate Design For Flip Chip Assembly
Author: Pericles A. Kondos
Abstract: Programs have been developed to predict the expected yield of flip chip assemblies, based on substrate design and the statistics of actual manufactured boards (e.g. in pad sizes and locations, mask registration, etc.), as well as placement machine accuracy, variations in bump sizes, and possible substrate warpage. These predictions and the trends they reveal can be used to direct changes in design so that defect levels will fall below the acceptable limits. Shapes of joints are calculated analytically, or when this is not possible, numerically by means of a public domain program called Surface Evolver. The method is illustrated with an example involving the substrates for a flip chip BGA. It was found that the original design would lead to unacceptably high defect levels, but alternative designs significantly improved the yield without creating other significant problems like bridging.
Flip Chip Assembly In Air: Effects On Eutectic Sn/Pb Solder Joint Formation And Reliability
Authors: Sandeep Tonapi and K. Srihari
Abstract: No-clean flip chip assembly processes usually involve reflow in a nitrogen ambient. This may, however, be expensive and not necessarily compatible with other SMT process recommendations. We present first results of efforts to develop a no-clean process involving reflow in air. The Kester TSF 6521 tacky flux here did not ensure complete collapse, causing concern with respect to assembly yields for some contact pad configurations. Also, air reflow led to a clear reduction in solder joint fatigue resistance. Efforts are under way to ascertain whether this may be remedied by a change of flux.
Lead-Free Flip Chip Assembly: An Overview
Authors: Sandeep Tonapi and K. Srihari
Abstract: This report addresses the effects of the reflow profile, pad metallurgy, and the amount of flux on the assembly of flip chips with lead-free solder bumps onto organic substrates. Four different lead-free alloys, namely, LF-1, LF-2, 95Sn/5Sb, and 91.8Sn/3.4Ag/4.8Bi were evaluated. The LF-1 alloy has a relatively low melting point of 197oC. Good wetting and a robust collapse could, however, not be achieved with flip chip relevant no-clean fluxes developed for eutectic Sn/Pb, even with peak reflow temperatures approaching 250oC. In fact, the other alloys performed much better at such temperatures. A reasonable and reproducible, but still not complete, collapse of the LF-2 joints was achieved for peak temperatures above 234oC. The Sn/Sb alloy offered full collapse but required a peak temperature of 250oC or more. Both the materials required relatively large amounts of flux, allowing for a quite narrow process window. The Sn/Ag/Bi alloy offered the most effective wetting and collapse, as well as the widest process window.
Liquid To Liquid Thermal Shock Testing Of Lf-1 Assemblies Underfilled With Dexter Fp4549
Authors: Sandeep Tonapi and K. Srihari
Abstract: Depending on the encapsulant edge fillet thickness, different damage mechanisms would contribute to assembly failure. Insufficient or excessive thickness would promote delamination progressing from the die corner to the solder joints. Failure of assemblies with intermediate fillet thicknesses was delayed and eventually caused by solder joint fatigue enhanced by local delamination.
Assembly Process Development For Flip Chips With Sn/Ag/Cu (Lf-2) Solder Bumps
Authors: Sandeep Tonapi and K. Srihari
Abstract: Imperfect soldering may be of concern for flip chip assembly for a variety of reasons. Even if the intermetallic bond is sufficient to ensure the robustness of the joints in an underfilled assembly, incomplete collapse may enhance the risk of an open connection. It may also enhance the scatter in the gaps to be underfilled and thus the scatter in the encapsulant edge fillet thicknesses. This may seriously affect assembly reliability.
8 mil perimeter array die with 4 mil tall bumps of the LF-2 (95.5Sn/3.5Ag/1.0Cu) alloy were assembled onto high–Tg FR-4 substrates using the Kester TSF6522 no-clean flux. Complete wetting and collapse required more flux than for eutectic Sn/Pb solder joints. However, unlike the LF-1 (85.9Sn/3.1Ag/10In/1.0Cu) alloy a relatively low peak reflow temperature and time above the liquidus appeared to be sufficient. The minor tendency for the LF-2 alloy to wet better to OSP coated copper pads than to Ni/Au was attributed to the variation in the pad sizes on the substrates with Ni/Au pads.
Liquid To Liquid Thermal Shock Testing Of Lf-2 Assemblies Underfilled With Namics U8437-3
Authors: Sandeep Tonapi and K. Srihari
Abstract: Depending on the encapsulant edge fillet thickness, different damage mechanisms would contribute to assembly failure. Insufficient or excessive thickness would promote delamination progressing from the die corner to the solder joints. Failure of assemblies with intermediate fillet thicknesses was delayed and eventually caused by solder joint fatigue enhanced by local delamination. The latter proved sensitive to the choice of flux and substrate pad metallurgy. Excellent thermal shock resistance was achieved by optimizing these parameters.
Effects Of Reflow Profile And Contact Pad Metallurgy On Lf-2 Flip Chip Solder Joint Properties
Authors: Sandeep Tonapi and K. Srihari
Abstract: 8 mil pitch perimeter array flip chip with 4 mil tall LF-2 (Sn/Ag/Cu) solder balls were reflow soldered onto pads on 62 mil thick FR-4 boards and tested in shear at room temperature. The total, combined, shear strength of the 88 joints in was found to exceed that of similar eutectic Sn/Pb joints. However, the strength was clearly sensitive to reflow profile, in particular for joints attached to Ni/Au-coated substrate pads. This raises concerns with regards to process control.
Thermal Cycling Resistance Of Sn/Pb And No-Pb Flip Chip Solder Joints
Authors: Sandeep Tonapi and K. Srihari
Abstract: The present work compares the thermal cycling resistance of flip chip solder joints in non-underfilled assemblies for two different substrate pad metallurgies and three different solder alloys. The results are consistent with behavior observed in shear testing and in cycling of underfilled assemblies. All the alloys proved sensitive to pad metallurgy. In the case of eutectic Sn/Pb, at least, this did not depend on substrate thickness. Differences between the alloys were smaller. However, indications are that the fatigue resistance of Sn/Ag/Cu joints may be sensitive to the reflow profile and that the consequences might depend on the thermal cycling conditions.
Author: Antonio Prats
Abstract: This report provides an overview of the heat spreader/lid attach efforts of the 2000 Area Array Consortium. It covers our understanding of the various factors that must be accounted for when designing the attach process. Some of the advantages and disadvantages of the various types of materials are discussed, along with an assessment of the effects of warpage. Finally, a case study is discussed, and recommendations for lid attach process design are summarized.
Author: Antonio Prats
Abstract: In preparation for the development of a lid attach process for a future commercial flip chip BGA package, four different approaches were tested with 6 different combinations of rim seal and thermal interface materials. Evaluation of the results show that the adhesive at the rim must be more or equally compliant to the attaching load than that at the die, in order to obtain good coverage and bondline thickness. In addition, the die design must allow the die to take up the load rather than causing it to be applied at the rim. If the lid adhesives are to be cured under load, the package must be well supported in the fixture to avoid warping the package.
Initial Studies Of Flip Chip Bga Heat Spreader Attachment
Authors: Balakrishnan Gopalan and K. Srihari
Abstract: This report summarizes a set of studies conducted on the attachment of heat spreaders to flip-chip packages. These experiments were targeted towards the identification of pertinent issues to be pursued in future work. Several attach methods were explored and adhesion to silicon, copper, and solder mask tested using Liquid-to-Liquid Thermal Shock. Case studies addressed effects of variations in the attachment to the substrate on the warpage of the assembly during reflow.
Process Development For Heat Spreader Attach Using A Liquid Adhesive
Authors: Balakrishnan Gopalan and K. Srihari
Abstract: This report summarizes the development of a heat spreader attach process for a product relevant flip-chip BGA test vehicle. The process involves dispensing a liquid adhesive and applying a specific load for a specific amount of time before cure. A process with a reasonably broad ‘window’ was developed, ensuring that warpage induced variations in rim seal thickness did not affect the thermal interface thickness appreciably.
Warpage Measurement Using A Flip Chip Bga Test Vehicle
Authors: Viraj Patwardhan, Antonio Prats and K. Srihari
Abstract: Warpage of the substrate at room temperature and warpage at reflow are concerns when estimating the assembly yields for surface mount devices. In the case of assemblies involving a chip carrier, the warpage of the substrate has several implications.
When attaching a lid to the flip chip, a warped coupon would have a reduced contact area between the seat of the lid and the substrate. This would result in a larger than expected volume for the lid attach material due to the wedge-shaped gap formed between the seat of the lid and the warped substrate. This warpage would, at the same time, reduce the gap between the top of the die and bottom of the lid compared to the designed gap.
The other concern regarding warpage arises during reflow. Here, the warpage of the component is different when compared to room temperature conditions, and may lead to a lack of contact between some solder bumps and their pads on the motherboard. These bumps may be the ones in the central region of the die or at the extreme ends, depending on the direction of warpage of the coupon.
This study attempts to obtain an understanding of these effects, in order to estimate the volume of adhesive to be dispensed in the lid seat area and over the top of the die. It also shows the possible effects of warpage when the component is placed onto the motherboard and passed through reflow.
Effect Of Heat Spreader Attach Process On The Reliability Of Flip Chip Devices
Authors: Balakrishnan Gopalan and K. Srihari
Abstract: Depending on the specific approach, the attachment of a heat spreader, or lid, to the back of an underfilled flip chip assembly invariably involves some level of mechanical deformation. The present work investigates the potential for this to damage the underfill, reducing its resistance to subsequent moisture exposure and thermal excursions.
Effect Of Torsion On The Reliability Of Flip Chip Devices
Authors: Balakrishnan Gopalan and K. Srihari
Abstract: This report investigates the effects of twist on first level reliability. The test vehicle was a polyimide passivated die on an FR4 substrate underfilled with Dexter FP4549. The preliminary study identified the limits of twist beyond which the encapsulant fillets would crack or the encapsulant delaminate. These were found to depend on the fillet thickness. In some cases, less twist was also found to damage the encapsulant-solder mask interface, leading to delamination there in subsequent cycling. This experiment also determined the degree of twist that caused ‘hair line cracks’. This also depends on the fillet thickness. The hair line cracks tended to enhance vertical cracking of the corner fillets and thus corner delamination.
Effect Of Torsion On The Reliability Of A Flip Chip Bga Test Vehicle
Authors: Balakrishnan Gopalan and K. Srihari
Abstract: Loading and deformation during heat spreader attach might conceivably damage the flip chip underfill. Seven different encapsulants were therefore compared in terms of their sensitivity to torsion (twist) in a particular FC-BGA package. For this purpose, the packages were first twisted to various degrees and then subjected to moisture exposure followed by Liquid-to-Liquid-Thermal-Shock, interrupting cycling at regular intervals to inspect for fillet cracking and delamination at both die and substrate solder mask surfaces. Based on the results three encapsulants – Namics XS8439-2, Thermoset ME525, and Honeywell JM8808 were selected for further investigation.
Area Array Consortium 2000 Flip Chip Research - An Overview
Author: Peter Borgesen
Abstract: Flip chip research conducted over the past year emphasized assembly, underfilling, lid attach and reliability. Assembly and underfilling studies included alternatives such as flux printing, reflow encapsulant and transfer molding based approaches. Reflow in air was seen to reduce assembly reliability and, presumably, assembly yields. Guidelines were developed for FC-BGA lid (heat spreader) design and attachment process development. Reliability studies aimed at completing our understanding of damage and failure mechanisms, as well as the effects of materials properties, interactions and compatibility. Aging and/or exposure to ambient humidity was seen to affect reliability very strongly. Current modeling was shown not to be consistent with well controlled model experiments, probably because of the unique loading modes in underfilled assemblies. A repairable underfill appeared moderately resistant to cycling with the appropriate chip passivation. Case studies demonstrated the use of available software in optimizing substrate design for assembly. High density substrates and inexpensive flex circuits were characterized in terms of parameters affecting such designs and assembly yields. Particular attention was paid to issues relating to the implementation of no-Pb soldering. This included assembly and metallurgical studies, as well as reliability testing. Issues were seen to be quite different from those identified in SMT, BGA and CSP applications.
Liquid Shock Testing Of 6 Mil Pitch Assemblies With The Kester 9101 Reflow Encapsulant
Authors: Viraj Patwardhan and K. Srihari
Abstract: The Kester 9101 reflow encapsulant was tested in Liquid-to-Liquid-Thermal Shock with 6 mil pitch nitride passivated flip chip on 40 mil thick FR-4 substrates. Testing led to cracking of the encapsulant in a variety of locations. First failure occurred after 1750-2000 cycles and 50% failure between 2750 and 3000 cycles. It may be possible to ensure life times in excess of 3250 cycles by proper control of the edge fillets near the die corners.
Assembling With Reflow Encapsulants: An Update
Author: Pericles A. Kondos
Abstract: Many builds with reflow encapsulants were made this year, using materials that had been tested before as well as several new materials from Dexter, Emerson & Cuming, Honeywell, Indium, Kester, and Sumitomo. The materials from Kester, Dexter, and Emerson & Cuming gave better results overall, while the others were in an early stage of development and needed further improvement. Among the first group of reflow encapsulants, the Kester 9101 and the two materials from Dexter have been used more extensively than the rest and have consistently given 100% soldering. The E&C and the Kester 9120 gave a small number of opens, which indicated that they were sensitive to the reflow profile. When the board was dried for a long time, or through a reflow before assembly, and used immedaitely, the assemblies were mostly void-free. When the underside of the die was contaminated, one of the Dexter materials gave voids, but not the E&C. Substrate drying still remains an issue.
Liquid Shock Testing Of An Experimental Kester Reflow Encapsulant In 6 Mil Pitch Assemblies
Authors: Viraj Patwardhan and K. Srihari
Abstract: Several different experimental reflow encapsulants from Kester were investigated. Only the LX1-95-1F soldered sufficiently well to also be submitted to reliability testing. The material performed comparably to other leading materials.
Authors: Viraj Patwardhan and K. Srihari
Abstract: 10 mil pitch flip-chips assembled on to 31 mil thick FR-4 boards using the Kester 9101 reflow encapsulant were tested in thermal cycling and thermal shock. Assemblies were monitored for fillet cracking, encapsulant delamination and solder joint failure. Electrical opens tended to occur without significant delamination, apparently correlated with edge fillet cracking. The statistics of failure were sensitive to the substrate pad metallurgy.
The encapsulant showed a tendency to crack, allowing solder extrusion and bridging along traces on the substrate. However, this seemed unique to the specific daisy chain design.
Flip Chip Reliability Overview
Author: Daniel L. Blass
Abstract: This report provides an overview of the flip chip reliability efforts of the 2000 Area Array Consortium. Much of the work focused on the prevention of fillet cracking and early chip failure from corner delamination. By controlling reliability experiments for the effects of fillet cracking, the optimum fillet thickness range can be determined along with the fatigue life for an underfill-flux combination. Various methods for accelerating the effects of moisture and aging on fillet cracking were investigated. Handling damage was investigated with an emphasis on the lid attach process. Some preliminary reliability experiments were conducted for a reworkable underfill, flip chip on flex, and chips assembled in air. Additional work investigated the reliability of chips built with two lead-free alloys.
Flip Chip Reliability Testing With An Emphasis On The Effect Of Fillet Thickness
Author: Daniel L. Blass
Abstract: Many factors play a role in flip chip reliability. The fillet thickness is one parameter that plays a critical role but normally is not adequately controlled in reliability experiments. This experiment is a model for how to properly conduct thermal cycle reliability experiments. Fillet thickness was varied in a set of flip chips to create a wide fillet thickness distribution. Solder joint failures were separated by the failure mode, either corner delamination or solder fatigue. By correlating corner delamination failures to fillet thickness, the experiment shows the optimum fillet thickness range. Different underfill-flux combinations can then be compared by the solder fatigue life and the optimum fillet thickness range. Preference should be given to underfills with a fillet thickness range that can easily be achieved in an automated underfill dispense process.
For many of the underfills, the best fillet thickness range was 4 and 14 mil thick. The Dexter FP4530 had the smallest thickness range, 4 to 12 mil thick. Sumitomo CRP4300-3 had the widest range with very thick fillets not giving corner delamination. Within the optimum range, Sumitomo CRP4056 and Dexter FP4549 gave solder fatigue failures between 2000 and 3000 cycles. Although no delamination was observed with the CRP4300-3, several fatigue failures occurred between 3000 and 4000 cycles. These failures were sensitive to the flux selection.
Effects Of Flux Residues On Liquid Shock Induced Failure Of Underfilled Flip Chip Assemblies
Authors: Sakethraman Mahalingam and K. Srihari
Abstract: No-clean flux residues are known to affect the reliability of underfilled flip chips in various ways. Not surprisingly, residues on and near the solder joints may affect delamination there quite strongly. However, residues have also been seen to affect edge fillet cracking as well as delamination near the die edges. Model experiments were conducted on flip chip assemblies underfilled with an unfilled epoxy to shed further light on this. Using a so-called reflow encapsulant both as intended and as a conventional underfill, effects of no-clean flux residues on delamination and electrical failure in liquid shock were quantified. The residues were seen to affect underfill delamination and edge fillet cracking at distances of more than 10 mil, but less than 65 mil, from the solder joints.
Accelerated Testing Of Flip Chip Assemblies Underfilled With Kester 9203 And Dexter Fp4549
Authors: Sakethraman Mahalingam and K. Srihari
Abstract: Aging and moisture degrade flip chip underfills and affect package reliability. These effects could be simulated by using aging/moisture preconditioning before reliability testing. This report investigates the effects of various moisture/aging preconditioning levels on one particular flip chip failure mechanism, fillet cracking.
Flip chip assemblies underfilled with Dexter FP4549 and Kester 9203 were exposed to three different moisture ambients for various times before Liquid to Liquid Thermal Shock (LLTS) testing. The fillets were inspected for cracking every 500 LLTS cycles. The cracking was also correlated to fillet thickness.
For medium fillet thicknesses, exposures to 80°C/60%R.H. accelerated fillet cracking by a factor of 3 compared to ambient “on the shelf” aging. 30°C/60%R.H. exposures and “on the shelf” aging gave similar fillet cracking. Thinner fillets were less likely to crack than thicker fillets but the various preconditions typically had stronger effects on thinner fillets. Flip chips aged several weeks “on the shelf” showed increased fillet cracking compared to non-preconditioned samples.
Preliminary Investigation Of Reliability Modeling Issues In Flip-Chip Solder Joints
Authors: James M. Pitarresi and Jin Zou
Abstract: The goal of this preliminary investigation was to study certain aspects that influence the mechanical reliability of underfilled flip-chip solder joints. Simple two- and three-dimensional finite element models of an underfilled assembly were built. The stress in the solder joints was computed as the package underwent a twenty-minute 0oC to 100oC temperature cycle. Three modeling configurations were investigated: fully underfilled assembly with complete adhesion between the solder and the underfill, fully underfilled assembly with no adhesion, and a partially underfilled assembly. The models showed that for the undefiled configuration, the normal stress dominated the solder response and that the stress distribution was independent of joint location. The fatigue life of the partially underfilled package was estimated from the three-dimensional models using Darveuax’s crack growth rate metric. However, this metric maybe too sensitive to shear stress in the solder joint. This sensitivity results in lower than expected solder joint life predictions. Caution should be exercised when using this approach for underfilled packages. It might be possible to modify Darveaux’s approach by adjusting the influence of shear and normal components to the crack growth rate equations. Further work needs to be done in order to understand this phenomenon.
Initial Screening Of 10 Underfills In Liquid-To-Liquid Thermal Shock
Authors: Sakethraman Mahalingam and K. Srihari
Abstract: Ten underfills materials were tested using Liquid-to-Liquid Thermal Shock (LLTS) between –55oC and 125oC. As an initial screening experiment, a small sample size was used and the failure mechanisms treated separately. All of the underfills showed some sensitivity to fillet cracking although not all gave corner delamination during thermal cycling. The best solder fatigue performance was observed for Emerson & Cuming E1252 with some of the chips surviving 4000 cycles. Considering the small sample sizes, most of the underfills showed comparable fatigue lives. Sumitomo CRP4055 and CRP4300-3 gave very little delamination but still failed before the E-1252.
Effect Of Local Underfill Adhesion On Solder Joint Fatigue In Flip Chip Assemblies
Authors: Sakethraman Mahalingam and K. Srihari
Abstract: All indications are that the progress of delamination, some of which is not measurable, may affect the fatigue of the solder joints in an underfilled flip chip assembly quite strongly. A quantitative life prediction would therefore have to include the prediction of delamination as well. This is, at best, a formidable task. An attempt was made to isolate the effects of delamination by underfilling model assemblies around the edges, outside the solder joint region, only. These were then cycled in Liquid Shock together with fully underfilled reference assemblies and the results compared in terms of absolute lifetimes and dependence on underfill materials properties. Surprisingly, an underfill material from Loctite with a relatively high CTE performed better than the Namics U8437-3 in both partially and fully underfilled assemblies. However, an extremely low CTE led to even better results in partially underfilled assemblies. The results should, at the very least, prove useful as a test of any proposed theoretical model.
Appendix To Flip Chip Reliability Overview
Author: Daniel L. Blass
Abstract: This appendix outlines our general picture of flip chip reliability. It covers our understanding of the various failure mechanisms that cause the solder joints to fail. The three most common failure modes are delamination enhanced solder fatigue, corner delamination caused by fillet cracking, and solder extrusion bridging. The various mechanical and chemical dependencies that affect reliability are also discussed.
"Effects Of Processing, Aging, And Thermal Cycling In Metal/Sn Systems: An Overview"
Authors: Anis Zribi, Richard Chromik, Lubov Zavalij and E. J. Cotts
Abstract: As briefly outlined in the present overview intermetallics formation in both no-Pb and Sn-based solder joints depends strongly on contact pad metallurgy and thermal history. The consequences for solder joint properties, both in the ‘bulk’ and at the pad surfaces, may be profound. Assembly robustness and reliability may be sensitive to both reflow profile and subsequent aging.
Reliability Of Model Flip Chip Assemblies On A Flex Substrate
Authors: Kevin J. Teed and K. Srihari
Abstract: Model flip chip assemblies were built on 4 mil thick polyimide flex substrates and subjected to liquid thermal shock testing. The substrate did not have a metal stiffener attached the back of the substrate under the chip area. The die were placed onto the flex and underfilled with Dexter CNB832-20 or Namics U8437-3. Underfill volume was varied to examine the effect of fillet thickness.
Underfill delamination from the solder joints was not observed for either underfill at the end of testing at 3000 LLTS cycles. Fillet cracking of the Dexter CNB832-20 caused corner delamination. The Dexter underfill also gave delamination from the chip passivation above the substrate pads. This may be a chemical effect, perhaps an incompatibility with the adhesive used to glue down the polyimide coverlay.
Fillet cracks were observed with both underfills. Namics U8437-3 followed the typical trend with thicker fillets having radial fillet cracks. For the Dexter, however, thinner fillets tended to crack. These were often cracks that propagated around the chip corner rather then radial fillet cracks. The Dexter fillet cracking appears to be handling related. Substrate stiffeners may be needed to prevent handling damage. More work is needed to investigate handling of flex substrates.
Horizontal die cracking was observed with the Namics underfill but not the Dexter. The Namics underfilled die were found to be more warped than the Dexter underfilled die.
Effect Of Substrate Thickness On Encapsulant Fillet Cracks In Flip Chip Devices
Authors: Balakrishnan Gopalan and K. Srihari
Abstract: This report addresses a particular effect of substrate thickness on first level reliability. The test vehicle was a polyimide passivated die on an FR4 substrate with a Taiyo PSR4000 solder mask. Namics U8437-3 material was used as the underfill encapsulant. Assemblies were exposed to 300C/60% R.H. for 192 hours, then cycled in Liquid-to-Liquid Thermal Shock. Thin substrates were seen to give more fillet cracks than thick ones. The difference was greatest for thicker fillets. Generally, thick fillets gave more cracks than thin ones for a particular substrate thickness.
Reliability Testing Of Loctite 3567 Reworkable Underfill
Author: Daniel L. Blass
Abstract: Reworkability has been a drawback to implementing flip chip on board in some applications. Once the underfill is cured, a defective chip could not be removed and replaced. Loctite has developed an underfill, Loctite 3567, which will break down at reflow temperatures and allow the chip or component to be removed. The underfill residue can be removed by mechanical brushing. Then a new component can be attached and underfilled.
This report investigates the reliability of Loctite 3567 with three packages, an electrically testable nitride-passivated flip chip, a polyimide-passivated flip chip, and a Flip Chip Technologies UltraCSP. The flip chips were tested in LLTS with and without moisture preconditioning for 8 days at 30°C/60%R.H. UltraCSPs were built with dip fluxing and tested in LLTS and air thermal cycling (0°C to 100°C). The effect of rework has not been considered.
The underfill showed poor fracture resistance with cracking in the fillets. Underfill cracks starting at the solder joints were also observed under the flip chips. These unusual cracks were enhanced by moisture preconditioning. Reliability in LLTS was comparable to unfilled reflow encapsulants. Adhesion to the BCB layer on the UltraCSP was poor. No fillet cracking was observed in the air cycle. Lifetimes of the Loctite 3567 underfilled CSPs were comparable to non-underfilled components.
Loctite 3567 is not a good choice for high reliability flip chip applications. It may be appropriate for lower reliability flip chip and CSP/BGA applications that require reworkability. If mechanical reliability is important, the brittle nature of the underfill should be considered when designing and evaluating reliability tests. While an underfilled component may pass a drop test, damage to the underfill could compromise subsequent thermal cycling performance.
Characterization Of An Adhesive Based Flex Substrate: A Case Study
Authors: Li - Yun Cheng and K. Srihari
Abstract: A 4 mil thick flex substrate made by Futura Circuits was characterized to study variations in pad width, adhesive "bleed out" onto the pads, size of the punched coverlay opening and registration of the opening to the copper circuits. The use of the punched coverlay to limit solderable copper area presents a number of challenges for flip chip assembly. Very poor tolerances were observed for several important substrate parameters.
The coverlay opening was designed to be 310 mil wide but averaged 308.9 mil with a standard deviation of 1.7 mil. One of the 32 openings was 301.7 mil, 9.3 mil smaller than designed. Adhesive bleed out onto the pads was as much as 6.7 mil with an average of 4.05 mil. Registration of the coverlay was poor as well with an average misregistration of almost 5 mil and the largest misregistration was more than 10 mil. The tolerances on the pad width were good with an average pad width of 6.02 mil with a standard deviation of 0.17 mil.
While the punched coverlay may be a very cheap way to make flexible substrates, an additional strategy must be used to limit solder collapse. Typical approaches use selective gold plating or limit solder wetting to OSP-coated copper by playing with the fluxing and reflow processes.
Characterization Of Flexible Circuits With Photoimageable Coverlays
Author: Daniel L. Blass
Abstract: Two flexible substrates were characterized to evaluate the size variation of the pads and coverlay openings. The registration of the coverlay to the copper circuits was also measured. Both substrates had photoimageable coverlays (PIC). The substrates were made by Innovex and Nitto Denko. Each substrate had several sites for flip chips and one site for a 0.5mm pitch CSP. Only the CSP site was characterized.
The registration of the PIC presents some problems for substrate design. Adapting typical mask layouts used for rigid boards would require using wide trench openings that would make larger than desired pads. Unless an additional strategy is used to limit collapse of the solder bumps, the resulting gap under the chip would be very small and difficult to underfill. To limit how far the solder wets out the traces, these substrates use an organic solderability protect pad finish called GLICOAT from Shikoku.
Characterization Of Ibiden Fr - 5 Substrates
Authors: Li - Yun Cheng, Manikandan Munikrishnan and K. Srihari
Abstract: Among a multitude of factors, the formation of a good solder joint in area array assembly depends on the substrate design parameters and their associated variations. Variations in the shapes, sizes or locations of the pads or solder mask openings could affect the manufacturing yield and the reliability. This should be taken into account when designing components and substrates for assembly.
The present study aimed at characterizing parameters of Ibiden FR-5 substrates that could affect placement and assembly yields. Features such as the pad size, solder mask opening size and the pad-to-mask mis-registration indicated tight tolerances with respect to variations. Both systematic and random variations were identified.
Transfer Molding Of Flip Chip Packages
Author: Daniel L. Blass
Abstract: This report is an overview of the research on transfer molding of flip chip packages. Working with several partners, flip chip parts were built and underfilled with transfer mold compounds from Dexter and Sumitomo. The main drawback so far is the inability to create a void free underfill layer. There are other avenues to pursue to achieve this, notably vacuum assisted molding and substrate venting. Limited JEDEC and LLTS test results are very encouraging. Parts were tested to 2000 LLTS cycles with no electrical failures although one part showed delamination originating at the chip corner. 16 of 17 parts passed JEDEC level 3 with a 240°C peak reflow temperature. Plasma cleaning and prebake are needed to assure good adhesion to the solder mask. The plasma cleaning process is sensitive to the flux type and the chip design.
Room Temperature Warpage Analysis Of Transfer Molded Flip Chip Bgas
Author: Antonio Prats
Abstract: Several sets of transfer molded flip chip components were measured to determine their room temperature warpage. All packages were warped in the same direction, and the warpage increased after the post-cure of the molding compound. One of the molding compounds produced packages with a higher degree of warpage than those made using either of the other two. The size of the die did not affect the measured warpage.
Location Of Indium Smq 75 Flux Residue In A Flip Chip Package
Authors: Szu-Wei Steve Yang, Denis C. Barbini and Wayne E. Jones
Abstract: Common failure mechanisms in flip chip packages are influenced by the flux residues left behind after reflow attach. It is generally believed that the underfill absorbs and/or reacts with the flux residues during the underfill and curing processes. Along with efforts to reduce the effect of these chemical products, it would be useful to identify the locations of flux residues before and after underfilling.
In this report, we describe several attempts to identify flux residue within a test flip chip package using Environmental Scanning Electron Microprobe- Energy Dispersion Spectroscopy (ESEM-EDS). Chemical phosphorus signals were used as a tracer since it was found in the residue of Indium SMQ 75 but not in the Dexter FP4549 underfill. Also, IR spectra was used to locate specific organic functional group signals in the flux residue.
The ESEM-EDS showed the phosphorus signals did not penetrate into the cured underfill layer. These were found to FTIR measurements in contrast, show evidence of an organic component to the SMQ 75 flux residue which sequesters to the chip side. There was no signature directly related to flux residue within the underfill matrix. Given the observation of two different flux residue components which behave differently, it would seem possible that one or more additional components of the flux residue may occur that are be absorbed by the underfill.
Effect Of The Underfill Dispense Pattern On Solder Extrusion
Authors: Sakethraman Mahalingam, Mukul Joshi and K. Srihari
Abstract: Solder extrusions require a small underfill void next to the solder joint. Often the voids occur in the solder mask openings next to the solder joint. Many variables affect the formation of underfill voids and solder extrusions. Along with the type of underfill, the flux, die layout, substrate design and dispense pattern can all affect the formation of underfill voids that allow solder extrusion.
This report examines the effect of two dispensing patterns on solder extrusion in a UIC flip chip assembly. The underfill was dispensed along one edge or dispensing along two edges in an L-shape. 15 underfills and 4 no-clean paste fluxes were used to build more than 1100 assemblies. The assemblies were subjected to JEDEC level 3 moisture sensitivity testing. The assemblies were then examined with an X-ray imaging system to observe solder extrusions that formed during reflow.
Along with the flux and underfill type, the formation of underfill voids that allow solder extrusions was sensitive to the dispense pattern. Of the two dispense patterns, the L-pattern usually gave fewer solder extrusions for this bump layout. Solder extrusion could have potentially been further reduced by choosing a pattern that allowed the underfill to flow through rather than along the denser rows of bumps.
Namics U8437-3 Fillet Thickness Control -- State Of The Art
Authors: Sakethraman Mahalingam and K. Srihari
Abstract: A total of 59 nominally identical full area array flip chip assemblies were underfilled with Namics U8437-3 by an expert practitioner using state of the art automated equipment. The thicknesses of the edge fillets at the corners of the assembly were characterized using a laser profilometer. Visual inspection suggested good uniformity. However, thicknesses were seen to vary between 2 and 12 mil across 40 assemblies underfilled with the same nominal volume and dispense pattern. Raising the dispense volume led to a range of 7-17 mil across the remaining 19 assemblies. Observed systematics suggest that it should be possible to reduce this to a range of, say, 5-10 mil by optimization of the materials selection and dispense process. It remains to be determined how practical such an optimization would be.
Authors: Sakethraman Mahalingam and K. Srihari
Abstract: The thicknesses of the underfill edge fillets, notably near the die corners, may affect the reliability of an underfilled flip chip assembly quite strongly. If a fillet is too thin, it may not exert enough compression on the chip passivation-underfill interface to prevent delamination along this. If, on the other hand, it is too thick it may tend to crack during thermal excursions, effectively eliminating the same compression. Depending on the assembly parameters and the underfill material, among other, ultimate thermal cycling performance may therefore only be achieved within a relatively narrow fillet thickness range. In the case of the Dexter FP4549 material, for example, the optimum range is usually between 2 and 9 mil. However, the fillet thicknesses achievable in an automated underfill process tend to vary for a number of reasons and it is by no means obvious to which extent they can be kept within the preferred range. This may have profound consequences for the preferred underfill material and recommended target fillet thickness in high reliability applications.
Three different underfill materials, Dexter FP4549, Honeywell 8802, and Kester 9203 were investigated in terms of dispense volume and distribution (flow) variations. The consequences of these and realistic gap size variations on achievable fillet thickness distributions were assessed for a representative example. The data should prove useful as representative input for such predictions for any other assembly designs as well.
Dispense Process Studies For Three Encapsulants Using Gpd Ds-9100
Authors: Ji Hyon Mun, Antonio Prats and K. Srihari
Abstract: One of the major concerns in flip chip assembly is the process of underfilling, especially with respect to the control of fillet thicknesses. Proper fillet thicknesses may be achievable with the selection of proper equipment and optimized operation, which depend on the encapsulant material and other factors associated with it. In this report, an effort has been made to evaluate the new dispensing machine, GPD DS-9100, and parameters controlling the dispensing of materials have been optimized for three encapsulant materials that exhibit unique characteristics. The effort made in this process was to optimize the operation to achieve a uniform dispense pattern with the required length and amount for only the three materials considered in this report. There was no prior process window developed for these materials using the DS-9100 dispenser. A 0.5 inch straight line was dispensed using a 25 gauge stainless steel needle for optimizing the operation. Then a different needle type was used to evaluate the change in the optimal process parameters.
Initial Screening Of Encapsulants For Self-Filleting
Authors: Ji Hyon Mun, Antonio Prats and K. Srihari
Abstract: It would often be attractive to eliminate the commonly recommended close-up pass when underfilling a flip chip assembly. This does, however, require the use of an encapsulant that is able to flow under the chip from the dispense edge(s) and climb up exit edges to form its own exit fillets there. We report of an initial set of screening experiments, covering a total of 25 materials, in order to identify those that show the potential for doing this.
Authors: Sakethraman Mahalingam, Mukul Joshi and K. Srihari
Abstract: Solder extrusion and bridging during thermal excursions is an assembly and reliability concern for flip chips. The root problem is the presence of small underfill voids near the solder joints. These voids form during underfilling and are most common in solder mask openings. Due to their small size and the location, these voids are difficult to detect with acoustic microscopy. If the flip chip is subjected to a reflow or thermal cycling, however, solder can flow or extrude into the void. Extrusions have been shown to weaken solder joints and cause faster fatigue. A greater concern is solder bridging because this causes a short circuit.
Previous work has shown voiding and solder extrusion to be very complicated. Many factors are important, including the bump layout, substrate and solder mask design, underfill, flux, pad finish, and solder alloy. The present work was conducted as a part of on-going efforts to understand the interaction of fluxes and underfills.
The present underfill-flux screening compares solder extrusion caused by the common package qualification test, the JEDEC Level 3 moisture sensitivity test. Flip chip assemblies were built with 4 no-clean fluxes and 15 underfills. Solder extrusions were observed after the JEDEC test with an X-ray imaging system.
Solder extrusion varied with underfill and flux type. More fluid underfills with lower particle loading and viscosity usually gave fewer extrusions but not always. The interaction between flux and underfill type was also important and many underfills were often more compatible with certain flux types. For most of the underfill-flux combinations, solder bridging was observed in at least one assembly.
Preliminary Investigation Of Automatic Exit Fillet Formation In Flip Chip Assemblies
Authors: Sandeep Tonapi and K. Srihari
Abstract: Overall underfill process throughput may be limited by the dispense time or flow time, depending on the number of flip chip assemblies in the dispenser at a time. In either case, it may often be significantly improved if a close-up pass can be avoided. Even moderate reliability applications do, however, require encapsulant fillets along all the four die edges. This report presents the results of initial experiments on automatic exit fillet formation. Exit fillet thicknesses were seen to be sensitive to the combination of encapsulant, flux type and solder mask.
Authors: Szu-Wei Steve Yang, Denis C. Barbini and Wayne E. Jones
Abstract: Failure and reliability studies in underfill materials require an examination of the chemical constituencies of the materials involved. The effects of chemical interactions under controlled variations of underfill and flux have now been investigated. Of particular interest is the effect of flux residue and acid content on underfill wetting. For traditional epoxy anhydride underfills, total acid content appears to have a significant affect on underfill wetting to a polyimide chip passivation. Cyanate Ester and ROMP materials appear to be less influenced under these conditions. The impact of residue content on the wetting of unfilled underfills is negligible. Residue content alone did not provide a means for monitoring trends in wetting.
Underfill Process Codification - 2000 Update
Authors: Antonio Prats, Peter Borgesen, Sandeep Tonapi, Pericles Kondos, Daniel Blass and K. Srihari
Abstract: The capillary flow-driven flip chip underfill process may be taken to include the selection of equipment (dispenser) and material. Creation of the process certainly involves specification of parameters such as bakeout requirements, substrate temperature, needle size, dispense paths (height above the substrate, distance to chip edge, length of pass), dispense rate, needle temperature, volume in each pass, timing of passes, cure parameters. Optimization of the process and specification of the process windows should minimize important variations and account for the inevitable variations (statistics and tolerances).
The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and troubleshooting. The establishment of a sizeable database is strongly recommended, through work done by your materials and equipment suppliers, or by yourself during final qualification or the development of processes for individual applications.
The individual sections of this document are carefully organized to minimize the amount of experimental work actually required to reach your goals.
Page updated
Google Sites
Report abuse